Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2705

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RE

S

E

R

V

E

D

0

ACCEPT_UNSOL

IC

ITED_RESP

O

NSE_ENABLE

RE

S

E

R

V

E

D

1

FLUS

H_CO

NTRO

L

CONTRO

LLER_RE

SET

31:9

0h

RO

reserved

8

0h

RW

If UNSOL is a 1 Unsolicited 

Responses from the codecs are accepted by the controller and placed into the Response 

Input Ring Buffer. If UNSOL is a 0 unsolicited responses are not accepted and dropped 

on the floor.

7:2

00h

RO

reserved

1

0h

RW

Writing a 1 to this bit initiates a flush. When the flush completion is 

received by the controller hardware sets the Flush Status bit and clears this Flush 

Control bit. Before a flush cycle is initiated the DMA Position Buffer must be 

programmed with a valid memory address by software but the DMA Position Buffer bit 0 

need not be set to enable the position reporting mechanism. Also all streams must be 

stopped the associated RUN bit must be 0 . When the flush is initiated the controller will 

flush pipelines to memory to guarantee that the hardware is ready to transition to a D3 

state. Setting this bit is not a critical step in the power state transition if the content of 

the FIFOs is not critical.

0

0h

RW

Writing a 0 to this bit causes the Intel HD Audio controller to be 

reset. All state machines FIFO s and non Suspend well memory mapped configuration 

registers except ECAP and PCI Configuration Registers in the controller will be reset. The 

Intel HD Audio link RESET signal will be asserted and all other link signals will be driven 

to their reset values. After the hardware has completed sequencing into the reset state 

it will report a 0 in this bit. Software must read a 0 from this bit to verify that the 

controller is in reset. Writing a 1 to this bit causes the controller to exit its reset state 

and de assert the Intel HD Audio link RESET signal. Software is responsible forsetting 

clearing this bit such that the minimum Intel HD Audio link RESET signal assertion pulse 

width specification is met. When the controller hardware is ready to begin operation it 

will report a1 in this bit. Software must read a 1 from this bit before accessing any 

controller registers. The CRST bit defaults to a 0 after hardware reset therefore software 

needs to write a 1 to this bit to begin operation. Note thatthe CORB RIRB RUN bits and 

all Stream RUN bits must be verified cleared to zero before CRST is written to 0 asserted 

in order to assure a clean re start. When setting or clearing CRST software must ensure 

that minimum link timing requirements minimum RESET assertion time etc. are met. 

When CRST is 0 indicating that the controller is in reset writes to all Intel HD Audio 

memory mapped registers are ignored as if the device is not present. The only exception 

is the Global Control register containing the CRST bit itself. The Global Control register is 

write able as a DWord Word or Byte even when CRST is 0 if the byte enable for the byte 

containing the CRST bit Byte Enable 0 is active. If Byte Enable 0 is not active writes to 

the Global Control register will be ignored when CRST is 0. When CRST is 0 reads to 

Intel HD Audio memory mapped registers will return their default value except for 

registers that are not reset with PLTRST or on a D3hot gt D0 transition.