Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2710
Datasheet
20.6.12
INTCTL—Offset 20h
Interrupt Control
Access Method
Default: 00000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
INTCTL:
AZLBAR Type:
PCI Configuration Register (Size: 32 bits)
AZLBAR Reference:
[B:0, D:27, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GL
OBAL_INTE
RRU
PT_E
NABLE
CONTRO
LLER_INTE
RRU
PT_E
NABLE
RESE
RVED
0
ST
REAM_INTE
RRU
PT_E
NABLE
Bit
Range
Default &
Access
Description
31
0h
RW
GLOBAL_INTERRUPT_ENABLE:
Global bit to enable device interrupt generation.
When set to 1 the Intel HD Audio function is enabled to generate an interrupt. This
control is in addition to any bits in the bus specific address space such as the Interrupt
Enable bit in the PCI Configuration Space. This bit is not affected by controller reset.
30
0h
RW
CONTROLLER_INTERRUPT_ENABLE:
Enables the general interrupt for controller
functions. When set to 1 and GIE is enabled the controller generates an interrupt when
the CIS bit gets set. This bit is not affected by controller reset.
29:8
0h
RO
RESERVED0:
reserved
7:0
00h
RW
STREAM_INTERRUPT_ENABLE:
When set to 1 the individual Streams are enabled to
generate an interrupt when the corresponding stream status bits get set. A stream
interrupt will be caused as a result of a buffer with IOC 1 in the BDL entry being
completed or as a result of a FIFO error underrun or overrun occurring. Control over the
generation of each of these sources is in the associated Stream Descriptor. The streams
are numbered and the SIE bits assigned sequentially based on their order in the register
set. Bit 0 Input Stream 1 Bit 1 Input Stream 2 Bit 2 Input Stream 3 Bit 3 Input Stream
4 Bit 4 Output Stream 1 Bit 5 Output Stream 2 Bit 6 Output Stream 3 Bit 7 Output
Stream 4