Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2713

Stream Synchronization

Default: 00000000h

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:27, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RESE

RVED

0

ST

R

E

AM_

S

Y

N

CH

R

O

NI

ZA

T

IO

N

_B

ITS

31:8

0h

RO

reserved

7:0

00h

RW

The Stream Synchronization bits when set to 1 

block data from being sent on or received from the link. Each bit controls the associated 

Stream Descriptor bit 0 corresponds to the first Stream Descriptor etc. To synchronously 

start a set of DMA engines the bits in the SSYNC register are first set to a 1. The RUN 

bits for the associated Stream Descriptors are then set to a 1 to start the DMA engines. 

When all streams are ready FIFORDY 1 the associated SSYNC bits can all be set to 0 at 

the same time and transmission or reception of bits to or from the link will begin 

together at the start of the next full link frame. To synchronously stop streams first the 

bits are set in the SSYNC register and then the individual RUN bits in the Stream 

Descriptors are cleared by software. The streams are numbered and the SSYNC bits 

assigned sequentially based on their order in the register set. Bit 0 Input Stream 1 Bit 1 

Input Stream 2 Bit 2 Input Stream 3 Bit 3 Input Stream 4 Bit 4 Output Stream 1 Bit 5 

Output Stream 2 Bit 6 Output Stream 3 Bit 7 Output Stream 4 Each bit can be reset by 

their respective stream reset.