Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
2714
Datasheet
20.6.16
CORBLBASE—Offset 40h
CORB Lower Base Address
Access Method
Default: 00000000h
20.6.17
CORBUBASE—Offset 44h
CORB Upper Base Address
Access Method
Default: 00000000h
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
CORBLBASE: 
AZLBAR Type: 
PCI Configuration Register (Size: 32 bits)
AZLBAR Reference: 
[B:0, D:27, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CO
R
B
_LOW
E
R
_B
AS
E_
AD
D
R
ESS
CORB_L
OWER_BASE
_
UN
IMPLEME
N
T
E
D_BIT
S
Bit 
Range
Default & 
Access
Description
31:7
0h
RW
CORB_LOWER_BASE_ADDRESS: 
Lower address of the Command Output Ring Buffer 
allowing the CORB Base Address to be assigned on any 64 B boundary. This register 
field must not be written when the DMA engine is running or the DMA transfer may be 
corrupted.
6:0
00h
RO
CORB_LOWER_BASE_UNIMPLEMENTED_BITS: 
Hardwired to 0. This requires the 
CORB to be allocated with 128 byte granularity to allow for cache line fetch 
optimizations.
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
CORBUBASE: 
AZLBAR Type: 
PCI Configuration Register (Size: 32 bits)
AZLBAR Reference: 
[B:0, D:27, F:0] + 10h