Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2715
20.6.18
CORBWP—Offset 48h
CORB Write Pointer
Access Method
Default: 0000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CORB_UPP
E
R
_BASE_ADDRE
S
S
Bit
Range
Default &
Access
Description
31:0
0h
RW
CORB_UPPER_BASE_ADDRESS:
Upper 32 bits of address of the Command Output
Ring Buffer. This register field must not be written when the DMA engine is running or
the DMA transfer may be corrupted.
Type:
Memory Mapped I/O Register
(Size: 16 bits)
CORBWP:
AZLBAR Type:
PCI Configuration Register (Size: 32 bits)
AZLBAR Reference:
[B:0, D:27, F:0] + 10h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESE
RVE
D
0
C
O
RB_WRITE_POINTE
R
Bit
Range
Default &
Access
Description
15:8
00h
RO
RESERVED0:
reserved
7:0
00h
RW
CORB_WRITE_POINTER:
Software writes the last valid CORB entry offset into this
field in Dword granularity. The DMA engine fetches commands from the CORB until the
Read Pointer matches the Write Pointer. Supports 256 CORB entries 256 x 4B 1KB . This
field may be written while the DMA engine is running.