Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2716
Datasheet
20.6.19
CORBRP—Offset 4Ah
CORB Read Pointer
Access Method
Default: 0000h
20.6.20
CORBCTL—Offset 4Ch
CORB Control
Access Method
Default: 00h
Type:
Memory Mapped I/O Register
(Size: 16 bits)
CORBRP:
AZLBAR Type:
PCI Configuration Register (Size: 32 bits)
AZLBAR Reference:
[B:0, D:27, F:0] + 10h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
O
RB_REA
D_P
O
INTER_RE
SET
RESE
RVED
0
CO
RB_REA
D
_
PO
INTER
Bit
Range
Default &
Access
Description
15
0h
RW
CORB_READ_POINTER_RESET:
Software writes a 1 to this bit to reset the CORB
Read Pointer to 0 and clear any residual pre fetched commands in the CORB hardware
buffer within the Intel Audio controller. The hardware will physically update this bit to 1
when the CORB Pointer reset is complete. Software must read a 1 to verify that the
reset completed correctly. Software must clear this bit back to 0 and read back the 0 to
verify that the clear completed correctly. The CORB DMA engine must be stopped prior
to resetting the Read Pointer or else DMA transfer may be corrupted.
14:8
00h
RO
RESERVED0:
reserved
7:0
00h
RO
CORB_READ_POINTER:
Software reads this field to determine how many commands
it can write to the CORB without over running. The value read indicates the CORB Read
Pointer offset in Dword granularity. The offset entry read from this field has been
successfully fetched by the DMA controller and may be over written by software.
Supports 256 CORB entries 256 x 4B 1KB . This field may be read while the DMA engine
is running.
Type:
Memory Mapped I/O Register
(Size: 8 bits)
CORBCTL:
AZLBAR Type:
PCI Configuration Register (Size: 32 bits)
AZLBAR Reference:
[B:0, D:27, F:0] + 10h