Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2719
20.6.23
RIRBLBASE—Offset 50h
RIRB Lower Base Address
Access Method
Default: 00000000h
3:2
0h
RO
RESERVED0:
reserved
1:0
02h
RO
CORB_SIZE:
Hardwired to 10b which sets the CORB size to 256 entries 1024B .
Bit
Range
Default &
Access
Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
RIRBLBASE:
AZLBAR Type:
PCI Configuration Register (Size: 32 bits)
AZLBAR Reference:
[B:0, D:27, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RIRB_L
O
W
ER_BA
S
E
_
ADDRE
S
S
RIRB
_
LOWER_BASE_UN
IMPLEME
NTED_BIT
S
Bit
Range
Default &
Access
Description
31:7
0h
RW
RIRB_LOWER_BASE_ADDRESS:
Lower address of the Response Input Ring Buffer
allowing the RIRB Base Address to be assigned on any 64 B boundary. This register field
must not be written when the DMA engine is running or the DMA transfer may be
corrupted.
6:0
00h
RO
RIRB_LOWER_BASE_UNIMPLEMENTED_BITS:
Hardwired to 0 to force 128 byte
buffer alignment for cache line fetch optimizations.