Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2727
20.6.32
ICS—Offset 68h
Immediate Command Status
Access Method
Default: 0000h
20.6.33
DPLBASE—Offset 70h
DMA Position Lower Base Address
Access Method
Default: 00000000h
Type:
Memory Mapped I/O Register
(Size: 16 bits)
ICS:
AZLBAR Type:
PCI Configuration Register (Size: 32 bits)
AZLBAR Reference:
[B:0, D:27, F:0] + 10h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESE
RVED
0
IMMEDIA
T
E_RESU
LT
_V
ALID
IMMEDIA
T
E_COMMAND_BUSY
Bit
Range
Default &
Access
Description
15:2
0000h
RO
RESERVED0:
reserved
1
0h
RW
IMMEDIATE_RESULT_VALID:
This bit is set to a 1 by hardware when a new response
is latched into the IRR register. This is a status flag indicating that software may read
the response from the Immediate Response register. Software must clear this bit by
writing a one to it before issuing a new command so that the software may determine
when a new response has arrived.
0
0h
RW
IMMEDIATE_COMMAND_BUSY:
When this bit as read as a 0 it indicates that a new
command may be issued using the Immediate Command mechanism. When this bit
transitions from a 0 to a 1 via software writing a 1 the controller issues the command
currently stored in the Immediate Command register to the codec over the link. When
the corresponding response is latched into the Immediate Response register the
controller hardware sets the IRV flag and clears the ICB bit back to 0. SW may write this
bit to a 0 if the bit fails to return to 0 after a reasonable timeout period. Note that an
Immediate Command must not be issued while the CORB RIRB mechanism is operating
otherwise the responses conflict. This must be enforced by software.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
DPLBASE:
AZLBAR Type:
PCI Configuration Register (Size: 32 bits)
AZLBAR Reference:
[B:0, D:27, F:0] + 10h