Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2742
Datasheet
20.6.49
ISD1FIFOS—Offset B0h
Input Stream Descriptor 1 FIFO Size
Access Method
Default: 0000h
20.6.50
ISD1FMT—Offset B2h
Input Stream Descriptor 1 Format
Access Method
Default: 0000h
Bit
Range
Default &
Access
Description
15:3
0000h
RO
RESERVED0:
reserved
2:0
04h
RO
FIFO_WATERMARK:
Indicates the minimum number of bytes accumulated in the FIFO
before the controller will start an eviction of data. The HD Audio controller hardwires the
FIFO Watermark either 32B or 64B based on the following. For input streams the FIFOW
value is determined by the EM3.ISRWS SEM3.ISRWS field.
Type:
Memory Mapped I/O Register
(Size: 16 bits)
AZLBAR Type:
PCI Configuration Register (Size: 32 bits)
AZLBAR Reference:
[B:0, D:27, F:0] + 10h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FIFO_SIZ
E
Bit
Range
Default &
Access
Description
15:0
00h
RW
FIFO_SIZE:
Indicates the maximum number of bytes that could be revicted by the
controller at one time. This is the maximum number of bytes that may have been
received from the link but not yet DMA d into memory and is also the maximum possible
value that the PICB count will increase by at one time. The FIFO size is calculated based
on factors including the stream format programmed in ISD1FMT register. As the default
value is zero, SW must write to the respective ISD1FMT register to kick of the FIFO size
calculation, and read back to find out the HW allocated FIFO size.
Type:
Memory Mapped I/O Register
(Size: 16 bits)
ISD1FMT:
AZLBAR Type:
PCI Configuration Register (Size: 32 bits)
AZLBAR Reference:
[B:0, D:27, F:0] + 10h