Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
System Memory Controller
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
275
Table 149. Memory Channel 0 DDR3L Signals (Sheet 1 of 2)
Signal Name
Direction
Type
Description
DRAM0_CKP[2,0]
DRAM0_CKN[2,0]
DRAM0_CKN[2,0]
O
DDR3
SDRAM and inverted Differential Clock: (1 pair per
Rank)
The differential clock pair is used to latch the command
into DRAM. Each pair corresponds to one rank on DRAM
side.
Rank)
The differential clock pair is used to latch the command
into DRAM. Each pair corresponds to one rank on DRAM
side.
DRAM0_CS[2,0]#
O
DDR3
Chip Select: (1 per Rank). Used to qualify the
command on the command bus for a particular rank.
command on the command bus for a particular rank.
DRAM0_CKE[2,0]
O
DDR3
Clock Enable: (power management)
It is used during DRAM power up/power down and Self
refresh.
Note: DDR3L uses only DRAM0_CKE[2,0].
DRAM0_CKE[1,3] are not being used for DDR3L.
It is used during DRAM power up/power down and Self
refresh.
Note: DDR3L uses only DRAM0_CKE[2,0].
DRAM0_CKE[1,3] are not being used for DDR3L.
DRAM0_MA[15:0]
O
DDR3
Memory Address: Memory address bus for writing
data to memory and reading data from memory. These
signals follow common clock protocol w.r.t.
DRAM0_CKN, DRAM0_CKP pairs
data to memory and reading data from memory. These
signals follow common clock protocol w.r.t.
DRAM0_CKN, DRAM0_CKP pairs
DRAM0_BS[2:0]
O
DDR3
Bank Select: These signals define which banks are
selected within each DRAM rank
selected within each DRAM rank
DRAM0_RAS#
O
DDR3
Row Address Select: Used with DRAM0_CAS# and
DRAM0_WE# (along with DRAM0_CS#) to define the
DRAM Commands
DRAM0_WE# (along with DRAM0_CS#) to define the
DRAM Commands
DRAM0_CAS#
O
DDR3
Column Address Select: Used with DRAM0_RAS#
and DRAM0_WE# (along with DRAM0_CS#) to define
the DRAM Commands
and DRAM0_WE# (along with DRAM0_CS#) to define
the DRAM Commands
DRAM0_WE#
O
DDR3
Write Enable Control Signal: Used with
DRAM0_WE# and DRAM0_CAS# (along with control
signal, DRAM0_CS#) to define the DRAM Commands.
DRAM0_WE# and DRAM0_CAS# (along with control
signal, DRAM0_CS#) to define the DRAM Commands.
DRAM0_DQ[63:0]
I/O
DDR3
Data Lines: Data signal interface to the DRAM data
bus
bus
DRAM0_DM[7:0]
O
DDR3
Data Mask: DM is an output mask signal for write
data. Output data is masked when DM is sampled HIGH
coincident with that output data during a Write access.
DM is sampled on both edges of DQS.
data. Output data is masked when DM is sampled HIGH
coincident with that output data during a Write access.
DM is sampled on both edges of DQS.
DRAM0_DQSP[7:0]
DRAM0_DQSN[7:0]
DRAM0_DQSN[7:0]
I/O
DDR3
Data Strobes: The data is captured at the crossing
point of each ‘P’ and its compliment ‘N’ during read and
write transactions.
For reads, the strobe crossover and data are edge
aligned, whereas in the Write command, the strobe
crossing is in the centre of the data window.
point of each ‘P’ and its compliment ‘N’ during read and
write transactions.
For reads, the strobe crossover and data are edge
aligned, whereas in the Write command, the strobe
crossing is in the centre of the data window.
DRAM0_ODT[2,0]
O
DDR3
On Die Termination: ODT signal going to DRAM in
order to turn ON the DRAM ODT during Write.
order to turn ON the DRAM ODT during Write.