Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2753
20.6.62
ISD3CTL_STS—Offset E0h
Input Stream Descriptor 3 Control and status
Access Method
Default: 00040000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
ISD3CTL_STS:
AZLBAR Type:
PCI Configuration Register (Size: 32 bits)
AZLBAR Reference:
[B:0, D:27, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESE
RVED
1
FIFO_RE
A
D
Y
DE
SCRIP
TO
R
_ERRO
R
FIFO
_ERRO
R
BUFFER_COMPLETIO
N
_INTE
RRUP
T
_ST
A
T
U
S
RESE
RVED
2
STRE
AM_NU
M
BE
R
BID
IRECTIO
NA
L_DI
R
E
CTIO
N_CO
NTRO
L
TRAFFIC_PRIORITY
S
T
RIP
E
_C
ONTROL
RESE
RVED
0
DES
C
RIPT
OR_E
RROR_INTE
RRU
PT_E
NABLE
FIFO_E
RROR_INTE
RRU
PT_E
NABLE
IN
T
E
RRUPT_ON_COMPLETION
_E
NABLE
STRE
AM_RU
N
ST
REAM_RE
S
ET
Bit
Range
Default &
Access
Description
31:30
0h
RO
RESERVED1:
reserved
29
0h
RO
FIFO_READY:
For input streams the controller hardware will set this bit to 1 when a
valid descriptor is loaded and the engine is ready for the RUN bit to be set.
28
0h
RW
DESCRIPTOR_ERROR:
Indicates that a serious error occurred during the fetch of a
descriptor. This could be a result of a Master Abort a Parity or ECC error on the bus or
any other error which renders the current Buffer Descriptor or Buffer Descriptor List
useless. This error is treated as a fatal stream error as the stream cannot continue
running. The RUN bit will be cleared and the stream will stop. Software may attempt to
restart the stream engine after addressing the cause of the error and writing a 1 to this
bit to clear it.
27
0h
RW
FIFO_ERROR:
Set when a FIFO error occurs. Bit is cleared by writing a 1 to this bit
position. This bit is set even if an interrupt is not enabled. For an input stream this
indicates a FIFO overrun occurring while the RUN bit is set. When this happens the FIFO
pointers don t increment and the incoming data is not written into the FIFO thereby
being lost.
26
0h
RW
BUFFER_COMPLETION_INTERRUPT_STATUS:
This bit is set to 1 by the hardware
after the last sample of a buffer has been processed AND if the Interrupt on Completion
IOC bit is set in the command byte of the buffer descriptor. It remains active until
software clears it by writing a 1 to this bit position.
25:24
0h
RO
RESERVED2:
reserved