Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2754

Datasheet

Input Stream Descriptor 3 Link Position in Buffer

Default: 00000000h

23:20

0h

RW

This value reflects the Tag associated with the data being 

transferred on the link. When an input stream is detected on any of the SDIx signals 

that match this value the data samples are loaded into the FIFO associated with this 

descriptor. Note that while a single SDIx input may contain data from more than one 

stream number two different SDIx inputs may not be configured with the same stream 

number. 0000 Reserved Indicates Unused 0001 Stream 1 1110 Stream 14 1111 Stream 

15

19

0h

RO

This bit is only meaningful for 

Bidirectional streams. Therefore this bit is hardwired to 0.

18

01h

RO

Hardwired to 1 indicating that all streams will use VC1 if it is 

enabled throughout the PCI Express registers.

17:16

0h

RO

This field is meaningless for input streams.

15:5

000h

RO

reserved

4

0h

RW

Controls whether an interrupt is 

generated when the Descriptor Error Status DESE bit is set.

3

0h

RW

This bit controls whether the occurrence of a 

FIFO error overrun for input will cause an interrupt or not. If this bit is not set bit 3 in 

the Status register will be set but the interrupt will not occur. Either way the samples will 

be dropped.

2

0h

RW

This bit controls whether or not an 

interrupt occurs when a buffer completes with the IOC bit set in its descriptor. If this bit 

is not set bit 2 in the Status register will be set but the interrupt will not occur.

1

0h

RW

When set to 1 the DMA engine associated with this input stream will be 

enabled to transfer data in the FIFO to main memory. The SSYNC bit must also be 

cleared in order for the DMA engine to run. When cleared to 0 the DMA engine 

associated with this input stream will be disabled. Hardware will report a 0 in this bit 

when the DMA engine is actually stopped. Software must read a 0 from this bit before 

modifying related control registers or restarting the DMA engine.

0

0h

RW

Writing a 1 causes the corresponding stream to be reset. The Stream 

Descriptor registers except the SRST bit itself and FIFO s for the corresponding stream 

are reset. After the stream hardware has completed sequencing into the reset state it 

will report a 1 in this bit. Software must read a 1 from this bit to verify that the stream 

is in reset. Writing a 0causes the corresponding stream to exit reset. When the stream 

hardware is ready to begin operation it will report a0 in this bit. Software must read a 0 

from this bit before accessing any of the stream registers. The RUN bit must be cleared 

before SRST is asserted.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:27, F:0] + 10h