Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

277

The system memory controller supports ECC. When ECC is enabled, only Memory 
Channel 0 will be active. Memory Channel 1 will be disabled and used for the ECC data 
signals. Signals on Memory Channel 1 not used for ECC will be tri-stated. The table 
below shows the details on the muxing relationship between the ECC signals and the 
Memory Channel 1 signals.

Although ECC and non-ECC SO-DIMM’s share the same socket, ECC SO-DIMMs are not 
pinout compatible with standard, non-ECC SO-DIMMs.

O

DDR3

Memory Address: Memory address bus for writing data 
to memory and reading data from memory. These signals 
follow common clock protocol relative to DRAM1_CKN, 
DRAM1_CKP pairs

O

DDR3

Bank Select: These signals define which banks are 
selected within each DRAM rank

O

DDR3

Row Address Select: Used with DRAM1_CAS# and 
DRAM1_WE# (along with DRAM1_CS#) to define the 
DRAM Commands

O

DDR3

Column Address Select: Used with DRAM1_RAS# and 
DRAM1_WE# (along with DRAM1_CS#) to define the 
DRAM Commands

O

DDR3

Write Enable Control Signal: Used with DRAM1_WE# 
and DRAM1_CAS# (along with control signal, 
DRAM1_CS#) to define the DRAM Commands.

I/O

DDR3

Data Lines: Data signal interface to the DRAM data bus.

O

DDR3

Data Mask: DM is an output mask signal for write data. 
Output data is masked when

 

DM is sampled HIGH 

coincident with that output data during a Write access. DM 
is sampled on both edges of DQS.

I/O

DDR3

Data Strobes: The data is captured at the crossing point 
of DRAM1_DQSP[7:0] and its compliment ‘N’ during read 
and write transactions.
For reads, the strobe crossover and data are edge aligned, 
whereas in the Write command, the strobe crossing is in 
the centre of the data window.

O

DDR3

On Die Termination: ODT signal going to DRAM in order 
to turn ON the DRAM ODT during Write.

O

Reset DRAM: This signal can be used to reset DRAM 
devices.