Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
2777
20.6.90
OSD2LPIB—Offset 144h
Output Stream Descriptor 2 Link Position in Buffer
Access Method
Default: 00000000h
4
0h
RW
DESCRIPTOR_ERROR_INTERRUPT_ENABLE: 
Controls whether an interrupt is 
generated when the Descriptor Error Status DESE bit is set.
3
0h
RW
FIFO_ERROR_INTERRUPT_ENABLE: 
This bit controls whether the occurrence of a 
FIFO error under run for output will cause an interrupt or not. If this bit is not set bit 3 
in the Status register will be set but the interrupt will not occur. Either way the samples 
will be dropped.
2
0h
RW
INTERRUPT_ON_COMPLETION_ENABLE: 
This bit controls whether or not an 
interrupt occurs when a buffer completes with the IOC bit set in its descriptor. If this bit 
is not set bit 2 in the Status register will be set but the interrupt will not occur.
1
0h
RW
STREAM_RUN: 
When set to 1 the DMA engine associated with this output stream will 
be enabled to transfer data in the main memory to FIFO. The SSYNC bit must also be 
cleared in order for the DMA engine to run. For output streams the cadence generator is 
reset whenever the RUN bit is set. When cleared to 0 the DMA engine associated with 
this output stream will be disabled. Hardware will report a 0 in this bit when the DMA 
engine is actually stopped. Software must read a 0 from this bit before modifying 
related control registers or restarting the DMA engine.
0
0h
RW
STREAM_RESET: 
Writing a 1 causes the corresponding stream to be reset. The Stream 
Descriptor registers except the SRST bit itself and FIFO s for the corresponding stream 
are reset. After the stream hardware has completed sequencing into the reset state it 
will report a 1 in this bit. Software must read a 1 from this bit to verify that the stream 
is in reset. Writing a 0causes the corresponding stream to exit reset. When the stream 
hardware is ready to begin operation it will report a0 in this bit. Software must read a 0 
from this bit before accessing any of the stream registers. The RUN bit must be cleared 
before SRST is asserted.
Bit 
Range
Default & 
Access
Description
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
OSD2LPIB: 
AZLBAR Type: 
PCI Configuration Register (Size: 32 bits)
AZLBAR Reference: 
[B:0, D:27, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LINK_POSITION_IN_BUFFER
Bit 
Range
Default & 
Access
Description
31:0
0h
RO
LINK_POSITION_IN_BUFFER: 
Indicates the number of bytes that have been 
received off the link. This register will count from 0 to the value in the Cyclic Buffer 
Length register and then wrap to 0.