Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2784
Datasheet
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RE
S
E
R
V
E
D
1
FIFO_REA
D
Y
DE
SCRIP
TO
R
_ERROR
FIFO
_ERROR
BUF
FER_C
OMPL
ETIO
N_INTE
RRUPT
_ST
A
TUS
RE
S
E
R
V
E
D
2
ST
R
E
AM_N
UMB
E
R
BIDIRE
C
T
IONAL_DIRE
CTION_CONTROL
TRAFFIC_PRIORITY
S
T
RIP
E
_C
ONTROL
RE
S
E
R
V
E
D
0
DES
C
RIPT
OR_E
RROR_INTE
RRU
PT_E
NABLE
FIFO_E
RROR_INTE
RRU
PT_E
NABLE
IN
T
E
RRUPT_ON_COMP
LE
TION
_E
NABLE
STRE
AM_RU
N
ST
REAM_RE
S
ET
Bit
Range
Default &
Access
Description
31:30
0h
RO
RESERVED1:
reserved
29
0h
RO
FIFO_READY:
For output streams the controller hardware will set this bit to a 1 while
the output DMA FIFO contains enough data to maintain the stream on then link. This bit
defaults to 0 on reset because the FIFO is cleared on a reset.
28
0h
RW
DESCRIPTOR_ERROR:
Indicates that a serious error occurred during the fetch of a
descriptor. This could be a result of a Master Abort a Parity or ECC error on the bus or
any other error which renders the current Buffer Descriptor or Buffer Descriptor List
useless. This error is treated as a fatal stream error as the stream cannot continue
running. The RUN bit will be cleared and the stream will stop. Software may attempt to
restart the stream engine after addressing the cause of the error and writing a 1 to this
bit to clear it.
27
0h
RW
FIFO_ERROR:
Set when a FIFO error occurs. Bit is cleared by writing a 1 to this bit
position. This bit is set even if an interrupt is not enabled. For an output stream this
indicates a FIFO under run when there are still buffers to send. The hardware should not
transmit anything on the link for the associated stream if there is not valid data to send.
26
0h
RW
BUFFER_COMPLETION_INTERRUPT_STATUS:
This bit is set to 1 by the hardware
after the last sample of a buffer has been processed AND if the Interrupt on Completion
IOC bit is set in the command byte of the buffer descriptor. It remains active until
software clears it by writing a 1 to this bit position.
25:24
0h
RO
RESERVED2:
reserved
23:20
0h
RW
STREAM_NUMBER:
This value reflects the Tag associated with the data being
transferred on the link. When data controlled by this descriptor is sent out over the link
it will have this stream number encoded on the SYNC signal. 0000 Reserved Indicates
Unused 0001 Stream 1 1110 Stream 14 1111 Stream 15
19
0h
RO
BIDIRECTIONAL_DIRECTION_CONTROL:
This bit is only meaningful for
Bidirectional streams. Therefore this bit is hardwired to 0.
18
01h
RO
TRAFFIC_PRIORITY:
Hardwired to 1 indicating that all streams will use VC1 if it is
enabled throughout the PCI Express registers.
17:16
0h
RO
STRIPE_CONTROL:
For output streams it controls the number of SDO signals to stripe
data across. Only one SDO is supported in the HD Audio controller. Therefore it is
hardwired to 0 s.
15:5
000h
RO
RESERVED0:
reserved