Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2801

The main DSP hardware is a two-multiplier, multiply/accumulate unit, a register file 
LPE_PR to hold pairs of 24-bit data items, a register file LPE-OR to hold 56-bit 
accumulator values, an arithmetic/logic unit to operate on the LPE_PR and LPE_OR 
values, and a shift unit to operate on the LPE_PR and LPE_OR values. The multiply/
accumulate unit also supports multiplication of 32-bit values from LPE_OR registers by 
16-bit values from LPE_PR registers, with the 48-bit result written or accumulated in 
the LPE_OR register. The instructions for the DSP subsystems are built from operations 
that are divided into two sets: the slot 0 set and the slot 1 set. In each execution cycle, 
zero or one operations from each set can be executed independently according to the 
static bundling expressed in the machine code.

The LPE core is configured to use local memory and local caches. It has 80KB of 
Instruction Closely Coupled Memory (CCM), 160KB of Data CCM, 48KB of Instruction 
Cache and 96KB of Data Cache. The LPE core also has access to 4KB of mailbox 
memory and external DRAM. 

SSP 0

Bridge

JTAG

JTAG
Trace

Logic

Interrupt

LPE

Core

EXT

I/F

LPE

Shim

Control & 

Config. Signals

A
U
D

I

O

  

S

u
b

F
a
b

r 

I 

c

Instruction 

RAM

Data RAM

64-bit

Data 

Cache

Instruction 

Cache

4KB

Mailbox

LPE

DMA_00

LPE

DMA_01

32-bit OCP Slave

32-bit APB Slave

32-bit OCP Master Writes

32-bit OCP Master Reads

32-bit OCP Slave

32-bit OCP Master Writes

32-bit OCP Master Reads

OCP

To/From 

IOSF2OCP bridge

M/N

CLK

SSP 1

M/N

CLK

32-bit APB Slave

SSP 2

M/N

CLK

32-bit APB Slave