Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Low Power Engine (LPE) for Audio (I
2
S)
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2803
21.3.3
Instruction Closely Coupled Memory (CCM)
Instruction CCM for the core is used for loading commonly used routines as well as
time-critical processing. Examples of time critical processing are acoustic echo
cancellation and noise cancellation during voice calls.
time-critical processing. Examples of time critical processing are acoustic echo
cancellation and noise cancellation during voice calls.
Instruction CCM is initialized after reset by an external DMA controller. Runtime update
of instruction CCM can be done either using explicit instructions or using an external
DMA controller with inbound access.
of instruction CCM can be done either using explicit instructions or using an external
DMA controller with inbound access.
21.3.4
Data Closely Coupled Memory (CCM)
Data CCM can be initialized after reset by an external DMA controller using inbound
access. Runtime update of data CCM can be done either using stores to Data CCM or
using an external DMA controller with inbound access.
access. Runtime update of data CCM can be done either using stores to Data CCM or
using an external DMA controller with inbound access.
21.3.5
Mailbox Memory and Data Exchange
The mailbox memory is a shared memory region in LPE address space that is accessible
by the SOC Processor Core, PMC, and LPE. It is used when Doorbell registers cannot
hold all the information that one processor wishes to communicate to the other. A
typical example of such data blocks are audio stream related parameters when starting
a new stream. The structures of data communicated through the mailbox are not
defined in hardware so that software may partition the mailbox memory in any desired
way and create any meaningful structures required.
by the SOC Processor Core, PMC, and LPE. It is used when Doorbell registers cannot
hold all the information that one processor wishes to communicate to the other. A
typical example of such data blocks are audio stream related parameters when starting
a new stream. The structures of data communicated through the mailbox are not
defined in hardware so that software may partition the mailbox memory in any desired
way and create any meaningful structures required.
21.4
Software Implementation Considerations
21.4.1
SoC Processor Core Cache Coherence
Traffic generated by the LPE core is considered non-cacheable and non-coherent with
respect to the SoC Processor Core cache. DMA traffic is considered cacheable and
checked for coherency with the SoC
respect to the SoC Processor Core cache. DMA traffic is considered cacheable and
checked for coherency with the SoC
Processor Core cache.
Implications of this implementation are as follows:
•
All code and tables for the LPE core need to be explicitly flushed from the SoC
Processor Core cache if they are ever accessed.
Processor Core cache if they are ever accessed.
•
If the LPE core directly accesses data buffers in system DDR, the driver must
explicitly flush the buffer from the SoC Processor Core cache
explicitly flush the buffer from the SoC Processor Core cache
•
If DMA accesses data buffers from system DRAM, the driver need not flush the data
buffer from the SoC Processor Core cache.
buffer from the SoC Processor Core cache.