Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Low Power Engine (LPE) for Audio (I
2
S)
Intel
®
Atom™ Processor E3800 Product Family
2804
Datasheet
21.4.2
Interrupts
21.4.2.1
LPE Peripheral Interrupts
Each of the LPE peripherals generates its own interrupts. SSP0, SSP1, and SSP2 have
one interrupt each. Each of the DMA channels have individual interrupt lines. These
interrupts are connected to the LPE core through the PISR register. The same interrupts
are routed to IOAPIC through the ISRX register. The LPE core and SoC Processor Core
have individual masks to enable these interrupts.
one interrupt each. Each of the DMA channels have individual interrupt lines. These
interrupts are connected to the LPE core through the PISR register. The same interrupts
are routed to IOAPIC through the ISRX register. The LPE core and SoC Processor Core
have individual masks to enable these interrupts.
21.4.2.2
Interrupts Between SoC Processor Core and the LPE
The interrupts between the SoC Processor Core and the LPE are handled through the
inter-processor communication registers. Whenever the SoC Processor Core writes to
the IPCX communication register an interrupt is generated to the LPE. The LPE
firmware sees there is a message waiting from the SoC Processor Core, and reads the
IPCX register for the data. This data is a pre-configured message, where the message
structure has been decided beforehand between the SoC Processor Core and the LPE.
Similarly we have the IPCD register for the communication between the LPE and SoC
Processor Core. Once the LPE writes to the IPCD register, an interrupt should be
generated for the SoC Processor Core and the SoC Processor Core should read the
message from the IPCD register and act accordingly. From a software viewpoint, the
mechanism remains the same as before. From a hardware view point, the interrupt to
IA-32 gets routed by means of the IOAPIC block. The IPC from Audio to SoC Processor
Core gets a dedicated interrupt line to the IOAPIC.
inter-processor communication registers. Whenever the SoC Processor Core writes to
the IPCX communication register an interrupt is generated to the LPE. The LPE
firmware sees there is a message waiting from the SoC Processor Core, and reads the
IPCX register for the data. This data is a pre-configured message, where the message
structure has been decided beforehand between the SoC Processor Core and the LPE.
Similarly we have the IPCD register for the communication between the LPE and SoC
Processor Core. Once the LPE writes to the IPCD register, an interrupt should be
generated for the SoC Processor Core and the SoC Processor Core should read the
message from the IPCD register and act accordingly. From a software viewpoint, the
mechanism remains the same as before. From a hardware view point, the interrupt to
IA-32 gets routed by means of the IOAPIC block. The IPC from Audio to SoC Processor
Core gets a dedicated interrupt line to the IOAPIC.
21.4.2.3
Interrupts between PMC and LPE
The interrupts between PMC and LPE are also handled using Inter Process
Communication registers.
Communication registers.
21.4.3
Power Management Options for the LPE Core
•
WAITI
— Allows the LPE core to suspend operation until an interrupt occurs by executing
the optional WAITI instruction.
•
External Run/Stall Control Signal
— This processor input allows external logic to stall large portions of the LPE
pipeline by shutting off the clock to much of the processor's logic to reduce
operating power when the LPE computational capabilities are not immediately
needed by the system.
operating power when the LPE computational capabilities are not immediately
needed by the system.
Note:
Using the WAITI instruction to power down the processor will save more power than
use of the external run/stall signal because the WAITI instruction disables more of the
LPE’s internal clocks.
use of the external run/stall signal because the WAITI instruction disables more of the
LPE’s internal clocks.