Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Low Power Engine (LPE) for Audio (I
2
S)
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2805
21.4.4
External Timer
This timer always runs from SSP clock (before M/N divider) at 19.2/25MHz. The timer
starts running once the run bit (refer to the External timer register definition for
details) is set and the clear bit is cleared.
starts running once the run bit (refer to the External timer register definition for
details) is set and the clear bit is cleared.
The timer generates an Interrupt pulse when the counter value matches the “match”
value. The interrupt does not get generated if the match value is set to “0”. The timer
runs in free running mode and rolls over after all 32 bits have become all 1’s.
value. The interrupt does not get generated if the match value is set to “0”. The timer
runs in free running mode and rolls over after all 32 bits have become all 1’s.
The timer continues to run as long as the run bit is set. Once the run bit is cleared the
timer holds the current value. The clear bit needs to be set to restart the timer from
“0”.
timer holds the current value. The clear bit needs to be set to restart the timer from
“0”.
21.5
Clocks
21.5.1
Clock Frequencies
shows the clock frequency options for the Audio functional blocks.
21.5.2
50 MHz Clock for LPE
50 MHz, the 2X OSC clock, is added to increase MIPS for low power MP3 mode. This
frequency will be supplied by the clock doubler internal to the SoC’s Clock Control Unit.
frequency will be supplied by the clock doubler internal to the SoC’s Clock Control Unit.
21.5.3
Cache and CCM Clocking
Data CCM, Data cache, Instruction CCM, and Instruction Cache run off of the LPE clock.
These memories are in a single clock domain.
These memories are in a single clock domain.
Note:
All Data CCM and Instruction CCM run in the same clock domain.
Table 225. Clock Frequencies
Clock
Frequency
Notes
Audio core
25/50/100/200/267/343 MHz
Audio input clock trunk. CCU drives
one of several frequencies as noted.
one of several frequencies as noted.
DMA 0
25/50 MHz
DMA clock
DMA1
25/50 MHz
DMA clock
Audio fabric clock
25/50 MHz
Fabric clock derived from audio core
clock
clock
SSP0 Clock
Fabric side: 25/50 MHz
Link side: Up to 19.2/25 MHz
Link side: Up to 19.2/25 MHz
SSP0 clock domains
SSP1 Clock
Fabric side: 25/50 MHz
Link side: Up to 19.2/25 MHz
Link side: Up to 19.2/25 MHz
SSP1 clock domains
SSP2 Clock
Fabric side: 25/50 MHz
Link side: Up to 19.2/25 MHz
Link side: Up to 19.2/25 MHz
SSP2 clock domains