Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Low Power Engine (LPE) for Audio (I
2
S)
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2807
The LPE M/N divider is designed to produce a clock signal for the SSP block used in
master mode. The divider is based on a generic NOM/DENOM divider. The supplied
Master clock is 25 MHz (XTAL) or 19.2 MHz (LPPLL), but usually be used by the 25 MHz
clock.
master mode. The divider is based on a generic NOM/DENOM divider. The supplied
Master clock is 25 MHz (XTAL) or 19.2 MHz (LPPLL), but usually be used by the 25 MHz
clock.
This mechanism is good for a wide spectrum of generated clocks. Two registers must be
configured to get the target SSP clock. The values for the Nominator and Denominator
registers are the smallest divider of:
configured to get the target SSP clock. The values for the Nominator and Denominator
registers are the smallest divider of:
21.5.5.1
Example
If we want to generate 17.64 MHz (=400x44.1 KHz) output clock out of 25 MHz clock,
we need to program “NOM = 441” and “DENOM = 625”:
we need to program “NOM = 441” and “DENOM = 625”:
17.64 MHz = (441/625) x 25 MHz
In general the M over N can generate fractional devisor that could be used for
generating the required clocks for Audio codec.
generating the required clocks for Audio codec.
describes some configuration
options of this generic divider:
21.5.5.2
Accuracy and Jitter
The output of the M/N is equal to the desired clock in average with Jitter of 20nTXE for
25 MHz input clock.
25 MHz input clock.
21.5.5.3
Configuration
Following configurable fields per M/N divider/SSP are in LPE shim registers:
Nominator
Denominator
=
Source_clock
Target_clock
Table 226. M/N Values, Examples
Source Clock
Frequency
Requested Clock
M/N Value
25 MHz
48 KHz
6/3125
48K x 24 = 1.152 MHz
1152/25000
48K x32 = 1.536 MHz
1536/25000
48K x 64 = 3.072 MHz
3072/25000
44.1 KHz
441/250000
48K x 400 = 19.2 MHz
96/125
44.1K x 400 = 17.64 MHz
441/625