Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Low Power Engine (LPE) for Audio (I
2
S)
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2809
•
12.5 Mbps maximum serial bit-rate in both modes: master and slave.
•
Clock master or slave mode operations
•
Receive-without-transmit operation
•
Network mode with up to eight time slots for PSP formats, and independent
transmit/receive in any/all/none of the time slots.
transmit/receive in any/all/none of the time slots.
•
After updating SSP configuration, for example active slot count, the SSP will need
to be disabled and enabled again. In other words, a SSP will not function correctly
if a user changes the configuration setting on the fly.
to be disabled and enabled again. In other words, a SSP will not function correctly
if a user changes the configuration setting on the fly.
21.6.3
Operation
Serial data is transferred between the LPE core or the SoC Processor Core and an
external peripheral through FIFOs in one of the SSP ports. Data transfers between an
SSP port and memory are initiated by either the LPE core or the SoC Processor Core
using programmed I/O, or by DMA bursts. Although it is possible to initiate transfers
directly from the SoC Processor Core, current driver design uses LPE for all PCM
operations. Separate transmit and receive FIFOs and serial data paths permit
simultaneous transfers in both directions to and from the external peripheral,
depending on the protocols chosen.
external peripheral through FIFOs in one of the SSP ports. Data transfers between an
SSP port and memory are initiated by either the LPE core or the SoC Processor Core
using programmed I/O, or by DMA bursts. Although it is possible to initiate transfers
directly from the SoC Processor Core, current driver design uses LPE for all PCM
operations. Separate transmit and receive FIFOs and serial data paths permit
simultaneous transfers in both directions to and from the external peripheral,
depending on the protocols chosen.
Programmed I/O can transfer data between:
•
The LPE core and the FIFO Data register for the TXFIFO
•
The SoC Processor Core and the FIFO Data register for the TXFIFO
•
The LPE core and the FIFO Data register for the RXFIFO
•
The SoC Processor Core and the FIFO Data register for the RXFIFO
•
The SoC Processor Core and the control or status registers
•
The LPE core and the control or status registers
DMA bursts can transfer data between:
•
Universal memory and the FIFO Data register for the TXFIFO
•
Universal memory and the FIFO Data register for the RXFIFO
•
Universal memory and the sequentially addressed control or status registers
21.6.4
LPE and DMA FIFO Access
The LPE or DMA access data through the Enhanced SSP Port’s Transmit and Receive
FIFOs. An LPE access takes the form of programmed I/O, transferring one FIFO entry
per access. LPE accesses would normally be triggered off of an SSSR Interrupt and
must always be 32 bits wide. LPE Writes to the FIFOs are 32 bits wide, but the
serializing logic will ignore all bits beyond the programmed FIFO data size (EDSS/DSS
value). LPE Reads to the FIFOs are also 32 bits wide, but the Receive data written into
the RX FIFO (from the RXD line) is stored with zeroes in the MSBs down to the
programmed data size. The FIFOs can also be accessed by DMA bursts, which must be
FIFOs. An LPE access takes the form of programmed I/O, transferring one FIFO entry
per access. LPE accesses would normally be triggered off of an SSSR Interrupt and
must always be 32 bits wide. LPE Writes to the FIFOs are 32 bits wide, but the
serializing logic will ignore all bits beyond the programmed FIFO data size (EDSS/DSS
value). LPE Reads to the FIFOs are also 32 bits wide, but the Receive data written into
the RX FIFO (from the RXD line) is stored with zeroes in the MSBs down to the
programmed data size. The FIFOs can also be accessed by DMA bursts, which must be