Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Low Power Engine (LPE) for Audio (I
2
S)
Intel
®
Atom™ Processor E3800 Product Family
2814
Datasheet
must always be 32 bits wide. The CPU Writes to the FIFOs are 32 bits wide, but the
serializing logic will ignore all bits beyond the programmed FIFO data size (EDSS/DSS
value). CPU Reads to the FIFOs are also 32 bits wide, but the Receive data written into
the RX FIFO (from the RXD line) is stored with zeroes in the MSBs down to the
programmed data size. The FIFOs can also be accessed by DMA bursts, which must be
in multiples of 1, 2, or 4 bytes, depending upon the EDSS value, and must also transfer
one FIFO entry per access. When the SSCR0.EDSS bit is set, DMA bursts must be in
multiples of 4 bytes (the DMA must have the Enhanced SSP configured as a 32-bit
peripheral). The DMA DCMD.width register must be at least the SSP data size
programmed into the SSP control registers EDSS and DSS. The FIFO is seen as one 32-
bit location by the processor. For Writes, the Enhanced SSP port takes the data from
the Transmit FIFO, serializes it, and sends it over the serial wire (I2Sx_DATAOUT) to
the external peripheral. Receive data from the external peripheral (on I2Sx_DATAIN) is
converted to parallel words and stored in the Receive FIFO.
serializing logic will ignore all bits beyond the programmed FIFO data size (EDSS/DSS
value). CPU Reads to the FIFOs are also 32 bits wide, but the Receive data written into
the RX FIFO (from the RXD line) is stored with zeroes in the MSBs down to the
programmed data size. The FIFOs can also be accessed by DMA bursts, which must be
in multiples of 1, 2, or 4 bytes, depending upon the EDSS value, and must also transfer
one FIFO entry per access. When the SSCR0.EDSS bit is set, DMA bursts must be in
multiples of 4 bytes (the DMA must have the Enhanced SSP configured as a 32-bit
peripheral). The DMA DCMD.width register must be at least the SSP data size
programmed into the SSP control registers EDSS and DSS. The FIFO is seen as one 32-
bit location by the processor. For Writes, the Enhanced SSP port takes the data from
the Transmit FIFO, serializes it, and sends it over the serial wire (I2Sx_DATAOUT) to
the external peripheral. Receive data from the external peripheral (on I2Sx_DATAIN) is
converted to parallel words and stored in the Receive FIFO.
A programmable FIFO trigger threshold, when exceeded, generates an Interrupt or
DMA service request that, if enabled, signals the IA-32 CPU or DMA respectively to
empty the Receive FIFO or to refill the Transmit FIFO. The Transmit and Receive FIFOs
are differentiated by whether the access is a Read or a Write transfer. Reads
automatically target the Receive FIFO, while Writes will write data to the Transmit FIFO.
From a memory-map perspective, they are at the same address. Each read or write is 1
SSP sample.
DMA service request that, if enabled, signals the IA-32 CPU or DMA respectively to
empty the Receive FIFO or to refill the Transmit FIFO. The Transmit and Receive FIFOs
are differentiated by whether the access is a Read or a Write transfer. Reads
automatically target the Receive FIFO, while Writes will write data to the Transmit FIFO.
From a memory-map perspective, they are at the same address. Each read or write is 1
SSP sample.
21.7.1
PIO and DMA Programming Considerations
All CPU and DMA accesses transfer one FIFO entry per access. Data in the FIFOs is
always stored with one 32-bit value per data sample, regardless of the format data
word length. Within each 32-bit field, the stored data sample is right-justified, with the
least significant bit of the word in bit 0. In the Receive FIFO, unused bits are packed as
zeroes above the most significant bit. In the Transmit FIFO, unused don’t-care bits are
above the most significant bit (i.e., DMA and CPU access do not have to write to the
unused bit locations). Logic in the Enhanced SSP automatically formats data in the
Transmit FIFO so that the sample is properly transmitted on I2Sx_DATAOUT in the
selected frame format.
always stored with one 32-bit value per data sample, regardless of the format data
word length. Within each 32-bit field, the stored data sample is right-justified, with the
least significant bit of the word in bit 0. In the Receive FIFO, unused bits are packed as
zeroes above the most significant bit. In the Transmit FIFO, unused don’t-care bits are
above the most significant bit (i.e., DMA and CPU access do not have to write to the
unused bit locations). Logic in the Enhanced SSP automatically formats data in the
Transmit FIFO so that the sample is properly transmitted on I2Sx_DATAOUT in the
selected frame format.
Two separate and independent FIFOs are present for Transmit (to peripheral) and
Receive (from peripheral) serial data. FIFOs are filled or emptied by programmed I/O or
DMA bursts.
Receive (from peripheral) serial data. FIFOs are filled or emptied by programmed I/O or
DMA bursts.
21.7.1.1
Programmed IO Considerations
FIFO filling and emptying can be performed by the processor in response to an
Interrupt from the FIFO logic. Each FIFO has a programmable FIFO trigger threshold at
which an Interrupt is triggered. When the number of entries in the Receive FIFO
exceeds the SSCR1.RFT value, an interrupt is generated (if enabled), which signals the
CPU to empty the Receive FIFO. When the number of entries in the Transmit FIFO is
less than or equal to the SSCR1.TFT value plus 1, an Interrupt is generated (if
enabled), which signals the CPU to refill the Transmit FIFO.
Interrupt from the FIFO logic. Each FIFO has a programmable FIFO trigger threshold at
which an Interrupt is triggered. When the number of entries in the Receive FIFO
exceeds the SSCR1.RFT value, an interrupt is generated (if enabled), which signals the
CPU to empty the Receive FIFO. When the number of entries in the Transmit FIFO is
less than or equal to the SSCR1.TFT value plus 1, an Interrupt is generated (if
enabled), which signals the CPU to refill the Transmit FIFO.