Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Low Power Engine (LPE) for Audio (I
2
S)
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2815
Users can also poll the Enhanced SSP Status register to determine how many samples
are in a FIFO, and whether the FIFO is full or empty. Software is responsible for
ensuring that the proper RFT and TFT values are chosen to prevent ROR and TUR error
conditions.
are in a FIFO, and whether the FIFO is full or empty. Software is responsible for
ensuring that the proper RFT and TFT values are chosen to prevent ROR and TUR error
conditions.
Note:
If the software attempts to read from an empty Receive FIFO, it will receive a duplicate
of the previously read value.
of the previously read value.
21.7.1.2
DMA Considerations
The DMA controller can also be programmed to transfer data to and from the Enhanced
SSP FIFOs. To prevent over-runs of the Transmit FIFO or under-runs of the Receive
FIFO when using the DMA, be careful when setting the Transmit and Receive FIFO
trigger threshold levels.
SSP FIFOs. To prevent over-runs of the Transmit FIFO or under-runs of the Receive
FIFO when using the DMA, be careful when setting the Transmit and Receive FIFO
trigger threshold levels.
There are restrictions on how the DMA can be programmed when used with the SSP
Controller.
Controller.
•
The DMA Transfer Width must be greater than or equal to the SSP data size. For
example if the SSP Data Size is 16b then the DMA Transfer Width should be 16b.
example if the SSP Data Size is 16b then the DMA Transfer Width should be 16b.
•
The DMA may not support the DMA Transfer Width of the SSP Data Size and
therefore the DMA Transfer Width must be larger than the SSP Data Size. If this is
the case then software must manage any extra data bits.
therefore the DMA Transfer Width must be larger than the SSP Data Size. If this is
the case then software must manage any extra data bits.
•
The DMA Burst Transaction Length for RX must be less than or equal to the RX
Threshold.
Threshold.
•
The DMA Burst Transaction Length for TX must be less than or equal to the number
of empty locations in the TX FIFO. A safe value is the Total TX FIFO Size - TX
Threshold.
of empty locations in the TX FIFO. A safe value is the Total TX FIFO Size - TX
Threshold.
•
DMA must be in Fixed Address mode to read or write the SSP Data Register.
In full-duplex formats where the Enhanced SSP always receives the same number of
data samples as it transmits, the DMA should be set up to transmit and receive the
same number of bytes.
data samples as it transmits, the DMA should be set up to transmit and receive the
same number of bytes.
Note:
A TFT value of 0 means that there is one sample left in the TX FIFO.
Because the Enhanced SSP is not flow controlled, software must program the TX FIFO
Threshold (TFT), RX FIFO Threshold (RFT), and the DMA burst size to ensure that a TX
FIFO overflow or RX FIFO underflow does not occur. Software must also ensure that the
Enhanced SSP DMA requests are properly prioritized in the system to prevent fatal
overruns and under-runs.
Threshold (TFT), RX FIFO Threshold (RFT), and the DMA burst size to ensure that a TX
FIFO overflow or RX FIFO underflow does not occur. Software must also ensure that the
Enhanced SSP DMA requests are properly prioritized in the system to prevent fatal
overruns and under-runs.
The programming model for using the DMA is as follows:
•
Program the total number of Transmit/Receive byte lengths, DMA burst, and DMA
Width in the DMA.
Width in the DMA.
•
Set the preferred values in the Enhanced SSP Control registers.
•
Enable the Enhanced SSP by setting SSCR0.SSE.
•
Set the run bit in DMA Command Register.