Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2834

Datasheet

POWERCAPID - PowerManagement Capability ID

Default: 00030001h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

MA

X

_

LA

T

MIN_G

N

T

Re

se

rv

ed

0

INTPIN

INTLINE

31:24

00h

RO

Value of 0 indicates device has no major requirements for the settings of 

latency timers

23:16

00h

RO

Value of 0 indicates device has no major requirements for the settings of 

latency timers

15:12

0h

RO

reserved

11:8

1h

RO

Interrupt Pin Value in this register is reflected from the IPIN value in the 

private configuration space. For a single function device, this ideally is INTA

7:0

00h

RW

Bridge does not use this field directly. It is used to communicate to software, 

the interrupt line to which the interrupt pin is connected.

Memory Mapped I/O Register

(Size: 32 bits)

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

PME

S

UP

PO

R

T

Re

se

rv

ed

0

VE

RSION

NX

TC

AP

PO

WE

R_CA

P

31:27

00h

RO

This 5-bit field indicates the power states in which the function can 

assert the PME#. A value of 0b for any bit indicates that the function is not capable of 

asserting the PME# signal at the same time in that power state. bit 11 X XXX1b: PME# 

can be asserted from D0 bit 12 X XX1Xb: PME# can be asserted from D1. Bridge does 

not support this state. bit 13 X X1XXb: PME# can be asserted from D2. Bridge does not 

support this state. bit 14 X 1XXXb:PME# can be asserted from D3hot bit 15 1 

XXXXb:PME# can be asserted from D3cold. Bridge does not support this state. This field 

is taken from the private configuration space PME_Support XORed with the 

PME_Support strap.

26:19

00h

RO

reserved

18:16

3h

RO

Indicates support for Revision 1.2 of the PCI Power Management 

Specification.