Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2838
Datasheet
21.11.1
reg_CSR_type (CSR)—Offset 0h
This register controls clock and reset of the block, various configurations of the block
and reflects general status of the block.
Access Method
Default: 0000000001E40001h
Type:
Memory Mapped I/O Register
(Size: 64 bits)
CSR:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
R
SVD
0
rs
vd_
0
R
SVD
1
rs
vd_
5
rs
vd_
6
rs
vd_
7
SS
P2
IO
C
LK
S
E
L
SS
P1
IO
C
LK
S
E
L
SS
P0
IO
C
LK
S
E
L
R
SVD
2
XT
_S
NP
Rs
vd_
1
Rs
vd_
2
Rs
vd_
3
R
SVD
3
SS
P2
b
as
ec
lk
se
l
SS
P1
b
as
ec
lk
se
l
SS
P0
b
as
ec
lk
se
l
PW
ai
tM
od
e
Ru
n
S
ta
ll
Sta
tV
ecto
rSe
l
LP
E
_
R
S
T
Bit
Range
Default &
Access
Description
63:32
0b
RO
RSVD0:
Reserved
31
0b
RW
rsvd_0:
Reserved
30:25
0b
RO
RSVD1:
Reserved
24
1b
RW
rsvd_5:
Reserved
23
1b
RW
rsvd_6:
Reserved
22
1b
RW
rsvd_7:
Reserved
21:20
10b
RW
SSP2IOCLKSEL:
SSP 2 IO clock select 0: select SSP 0 IO clock for SSP 2 IO clock input
1: select SSP 1 IO clock for SSP 2 IO clock input 2: select SSP 2 IO clock for SSP 2 IO
clock input
19:18
01b
RW
SSP1IOCLKSEL:
SSP 1 IO clock select 0: select SSP 0 IO clock for SSP 1 IO clock input
1: select SSP 1 IO clock for SSP 1 IO clock input 2: select SSP 2 IO clock for SSP 1 IO
clock input
17:16
00b
RW
SSP0IOCLKSEL:
SSP 0 IO clock select 0: select SSP 0 IO clock for SSP 0 IO clock input
1: select SSP 1 IO clock for SSP 0 IO clock input 2: select SSP 2 IO clock for SSP 0 IO
clock input
15:12
0b
RO
RSVD2:
Reserved
11
0b
RW
XT_SNP:
This bit controls whether the Tensilica initiated traffic is Snooped or Non-
snooped. 0 =) Non-Snooped 1 =) Snooped
10
0b
RW
Rsvd_1:
Reserved
9
0b
RW
Rsvd_2:
Reserved