Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2846
Datasheet
21.11.9
reg_IPCD_type (IPCD)—Offset 40h
Inter-process Status and Message register for LPE contains a message sent from LPE to
IA-32 CPU. The format of the CPU message bits 29:0 is defined in the LPE Firmware
specifications. The message may contain optional data fields stored in the shared
memory region (mailbox). When software writes the message is in this register, it
should set bit 63 to indicate that the new data is written. When IA-32 CPU reads the
message code from the register, and writes back with the bit 63 cleared. When the IA-
32 CPU processes the message sent by LPE, it may set bit 63 in IPCD to assert
interrupt request to LPE. The LPE must not attempt to write into IPCLPEIA if bit 63 is
set.
Access Method
Default: 0000000000000000h
21.11.10 reg_ISRSC_type (ISRSC)—Offset 48h
ISRSC
Access Method
62
0b
RW
LPE_IA_DONE:
Done. When the bit is set, the LPE completed the operation and
requests attention
61:0
000000000
0000000h
RW
IA_LPE_MSG:
IA-32 to LPE Message
Bit
Range
Default &
Access
Description
Type:
Memory Mapped I/O Register
(Size: 64 bits)
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LP
E_I
A
_B
US
Y
IA_
LP
E
_DONE
LP
E
_
IA
_M
SG
Bit
Range
Default &
Access
Description
63
0b
RW
LPE_IA_BUSY:
Busy. When this bit is cleared, the IA CPU is Ready to accept a new
message
62
0b
RW
IA_LPE_DONE:
Done. When the bit is set, the IA CPU completed operation and
requests attention from LPE
61:0
000000000
0000000h
RW
LPE_IA_MSG:
LPE to IA CPU Message