Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2848
Datasheet
21.11.12 reg_IMRSC_type (IMRSC)—Offset 58h
IMRSC
Access Method
Default: 0000000000000000h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD0
S
C
_L
PE_
IPC
_
R
equ
est
_S
ta
tu
s
SC
_
LP
E
_I
PC
_D
o
n
e_
S
ta
tu
s
Bit
Range
Default &
Access
Description
63:2
0b
RO
RSVD0:
Reserved
1
0b
RO
SC_LPE_IPC_Request_Status:
IPCSC Interrupt Request to LPE 1: interrupt when SC
writes a message into IPCSC register with bit 63 set. 0: Deasserted
0
0b
RO
SC_LPE_IPC_Done_Status:
IPCLPESC Interrupt Request to LPE 1: interrupt when SC
CPU writes a message into IPCLPEIA register with bit 62 set is asserted 0: Deasserted.
Type:
Memory Mapped I/O Register
(Size: 64 bits)
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
SVD0
Go
S0
ix_
IntE
n
Fa
b
D
is
ab
le
Go
S0
ixIn
t_
SC
U_M
ask
R
SVD1
LP
E_
SC
_I
PC
_R
eq
u
es
t_
M
as
k
LP
E
_
S
C
_I
PC
_
D
on
e_
Mas
k
Bit
Range
Default &
Access
Description
63:35
0b
RO
RSVD0:
Reserved
34
0b
RW/1C
GoS0ix_IntEn:
This bit indicates that Reentry to S0iX interrupts to SCU are enabled.
The bit is set by hardware when a transaction is blocked at the Audio to Secondary
interface due to the secondary fabric being gated and the fabdisable bit being set.
Software is expected to clear this bit along with the Secondary Fabric Reject bit. This
disables the interrupts.