Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2850
Datasheet
empty. Setting Busy also asserts interrupt request to LPE if the interrupt is enabled in
the IMRLPESC. After LPE reads the message code from the register, it must perform a
write with bit 63 cleared. The SC CPU must not attempt to write into IPCIA if bit 63 is
set.
Access Method
Default: 0000000000000000h
21.11.15 reg_IPCLPESC_type (IPCLPESC)—Offset 70h
Inter-process Status and Message register for LPE contains a message sent from LPE to
SC. The format of the CPU message bits 29:0 is defined in the LPE Firmware
specifications. The message may contain optional data fields stored in the shared
memory region (mailbox). When software writes the message is in this register, it
should set bit 63 to indicate that the new data is written. When SC reads the message
code from the register, and writes back with the bit 63 cleared. When the SC CPU
processes the message sent by LPE, it may set bit 62 in IPCLPESC to assert interrupt
request to LPE. The LPE must not attempt to write into IPCD if bit 63 is set.
Access Method
Default: 0000000000000000h
Type:
Memory Mapped I/O Register
(Size: 64 bits)
IPCSC:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SC
_
LPE
_B
USY
LP
E_S
C
_D
O
N
E
SC
_LP
E
_M
S
G
Bit
Range
Default &
Access
Description
63
0b
RW
SC_LPE_BUSY:
Busy. When this bit is cleared, the LPE Ready to accept a message
62
0b
RW
LPE_SC_DONE:
Done. When the bit is set, the LPE completed the operation and
requests attention
61:0
000000000
0000000h
RW
SC_LPE_MSG:
SC to LPE Message
Type:
Memory Mapped I/O Register
(Size: 64 bits)
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h