Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2853
Access Method
Default: 0000000000000000h
21.11.19 reg_ISRPSH_type (ISRPSH)—Offset 90h
ISRPSH
Access Method
Default: 0000000000000000h
Type:
Memory Mapped I/O Register
(Size: 64 bits)
CHICKEN_BITS:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSV
D
0
DMA
_
Debug
_
Select
XT
_p
ost
ed
_
o
n
ly
_t
ra
ffic
IP
C
_
w
ak
es_S
C
U
bu
g_
24
31
32
9
_
fi
x_d
isa
b
le
disab
le
_
ssp
2_
dma_
fin
ish
disab
le
_
ssp
1_
dma_
fin
ish
disab
le
_
ssp
0_
dma_
fin
ish
wai
ti_
fi
x_e
n
ab
le
Bit
Range
Default &
Access
Description
63:8
0b
RO
RSVD0:
Reserved
7
0b
RW
DMA_Debug_Select:
Setting this bit will select DMA 1 debug signals to be routed to
the VISA Mux.
6
0b
RW
XT_posted_only_traffic:
Setting this bit will select make all the traffic from Tensilica
to be posted.
5
0b
RW
IPC_wakes_SCU:
Setting this to 1 will cause the IPC to be fed into the wake cone for
SCU.
4
0b
RW
bug_2431329_fix_disable:
Setting this to 1 will disable the synopsys compatible
hardware handshake mechanism. Keep this set to 0 for regular hardware handshake
operation.
3
0b
RW
disable_ssp2_dma_finish:
Setting this to 1 will cause the SSP Unit to ignore the
dma_finish signal. Set this to 1 for MultiBlock transfers.
2
0b
RW
disable_ssp1_dma_finish:
Setting this to 1 will cause the SSP Unit to ignore the
dma_finish signal. Set this to 1 for MultiBlock transfers.
1
0b
RW
disable_ssp0_dma_finish:
Setting this to 1 will cause the SSP Unit to ignore the
dma_finish signal. Set this to 1 for MultiBlock transfers.
0
0b
RW
waiti_fix_enable:
Setting this bit to 1 makes the frequency change request to be valid
only if the core is in WAITI.
Type:
Memory Mapped I/O Register
(Size: 64 bits)
ISRPSH:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h