Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2857
21.11.24 reg_IPCLPEPSH_type (IPCLPEPSH)—Offset B8h
Inter-process Status and Message register for LPE contains a message sent from LPE to
PSH. The format of the CPU message bits 29:0 is defined in the LPE Firmware
specifications. The message may contain optional data fields stored in the shared
memory region (mailbox). When software writes the message is in this register, it
should set bit 63 to indicate that the new data is written. When PSH reads the message
code from the register, and writes back with the bit 63 cleared. When the PSH CPU
processes the message sent by LPE, it may set bit 62 in IPCLPEPSH to assert interrupt
request to LPE. The LPE must not attempt to write into IPCD if bit 63 is set.
Access Method
Default: 0000000000000000h
21.11.25 reg_EXT_TIMER_CNTL_type (EXT_TIMER_CNTL)—Offset C0h
External Timer Control Register
Access Method
62
0b
RW
LPE_PSH_DONE:
Done. When the bit is set, the LPE completed the operation and
requests attention
61:0
000000000
0000000h
RW
PSH_LPE_MSG:
PSH to LPE Message
Bit
Range
Default &
Access
Description
Type:
Memory Mapped I/O Register
(Size: 64 bits)
IPCLPEPSH:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LP
E
_
PS
H
_
BU
S
Y
PS
H_L
PE_
DO
NE
LP
E_P
S
H
_
MSG
Bit
Range
Default &
Access
Description
63
0b
RW
LPE_PSH_BUSY:
Busy. When this bit is cleared, the PSH CPU is Ready to accept a new
message
62
0b
RW
PSH_LPE_DONE:
Done. When the bit is set, the PSH CPU completed operation and
requests attention from LPE
61:0
0h
RW
LPE_PSH_MSG:
LPE to PSH CPU Message
Type:
Memory Mapped I/O Register
(Size: 64 bits)
EXT_TIMER_CNTL:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h