Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2858
Datasheet
Default: 0000000000000000h
21.11.26 reg_EXT_TIMER_STAT_type (EXT_TIMER_STAT)—Offset C8h
External Timer Control Register
Access Method
Default: 0000000000000000h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Ext_
Ti
me
r_
R
u
n
Ext
_
T
im
er
_
Cl
ear
RS
VD0
Ext
_
T
im
er
_
M
atch
value
Bit
Range
Default &
Access
Description
63
0b
RW
Ext_Timer_Run:
Timer Run bit. The timer runs only when this bit is set. It resumes
running from the current value in the readvalue bits. Clearing the bit pauses the timer.
62
0b
RW/S
Ext_Timer_Clear:
Timer Clear bit. Clears the timer and sets the value back to zero.
This should also be reflected in the readvalue bits
61:32
0b
RO
RSVD0:
Reserved
31:0
0b
RW
Ext_Timer_Matchvalue:
The timer will generate a pulse when the Readvalue reaches
Matchvalue. The pulse causes a level interrupt to get set in the PISR register. The PISR
interrupt needs to be cleared before the next pulse is generated. The timer keeps
counting beyond the Readvalue. Setting the Matchvalue to zero makes this a free
running timer and no interrupt will be generated in this case. For correct operation, the
ISR should either set a new Matchvalue or set it to zero. If nothing is done, the timer will
roll over and trigger an interrupt again when it reaches the Matchvalue.
Type:
Memory Mapped I/O Register
(Size: 64 bits)
EXT_TIMER_STAT:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
SVD0
Ext
_
T
im
er
_
R
eadv
alue
Bit
Range
Default &
Access
Description
63:32
0b
RO
RSVD0:
Reserved