Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2859

External Timer Control Register

Default: 0000000000000000h

External Timer Control Register

Default: 0000000000000000h

31:0

0b

RO

Shows the current count value of the timer

Memory Mapped I/O Register

(Size: 64 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:21, F:0] + 10h

6

3

6

0

5

6

5

2

4

8

4

4

4

0

3

6

3

2

2

8

2

4

2

0

1

6

1

2

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

S

0

ix

_T

im

er

_R

u

n

S

0

ix

_T

ime

r_C

le

ar

RS

VD0

S0

ix

_T

ime

r_Ma

tch

va

lu

e

63

0b

RW

Timer Run bit. The timer runs only when this bit is set. It resumes 

running from the current value in the readvalue bits. Clearing the bit pauses the timer.

62

0b

RW/S

Timer Clear bit. Clears the timer and sets the value back to zero. 

This should also be reflected in the readvalue bits

61:32

0b

RO

Reserved

31:0

0b

RW

The timer will generate a pulse when the Readvalue reaches 

Matchvalue. The pulse causes a level interrupt to get set in the PISR register. The PISR 

interrupt needs to be cleared before the next pulse is generated. The timer keeps 

counting beyond the Readvalue. Setting the Matchvalue to zero makes this a free 

running timer and no interrupt will be generated in this case. For correct operation, the 

ISR should either set a new Matchvalue or set it to zero. If nothing is done, the timer will 

roll over and trigger an interrupt again when it reaches the Matchvalue.

Memory Mapped I/O Register

(Size: 64 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:21, F:0] + 10h