Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2862
Datasheet
21.11.31 reg_SSP1_DIV_CTRL_type (SSP1_DIV_CTRL)—Offset F0h
SSP1 M/N Clock Divider control - Add for VLV
Access Method
Default: 8000000100000001h
21.11.32 reg_SSP2_DIV_CTRL_type (SSP2_DIV_CTRL)—Offset F8h
SSP2 M/N Clock Divider control - Add for VLV
Access Method
Default: 8000000100000001h
Type:
Memory Mapped I/O Register
(Size: 64 bits)
SSP1_DIV_CTRL:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Di
vi
de
r_B
ypa
ss
Di
vid
er_
En
Div
ider
_
Upd
ate
RS
VD0
Di
vid
er_M
RS
VD1
Div
ider
_
N
Bit
Range
Default &
Access
Description
63
1b
RW
Divider_Bypass:
SSP1 Bypass divider
62
0b
RW
Divider_En:
SSP1 Enable divider
61
0b
RW
Divider_Update:
SSP1 Update divider
60:52
0b
RO
RSVD0:
Reserved
51:32
1b
RW
Divider_M:
SSP1 Nominator value
31:20
0b
RO
RSVD1:
Reserved
19:0
1b
RW
Divider_N:
SSP1 Denominator value
Type:
Memory Mapped I/O Register
(Size: 64 bits)
SSP2_DIV_CTRL:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h