Intel E3815 FH8065301567411 Data Sheet

Product codes

FH8065301567411

Intel

Atom™ Processor E3800 Product Family

2864

Datasheet

21.12

Low Power Audio I

S0 Address Map

21.12.1

SSP Control 0 Register (SSCR0)—Offset 0h

The Enhanced SSP Control 0 registers contain twelve different bit fields that control

various functions within the Enhanced SSP. All bits must be set to the preferred value

before enabling the Enhanced SSP. Note that Writes to reserved bits must be zeroes,

and Read values of these bits is undetermined.

Access Method

Default: 00000000h

Table 232.

Summary of Low Power Audio I

S0 Memory Mapped I/O Registers—BAR

Offset

Size

Register ID—Description

Default

Value

“SSP Control 0 Register (SSCR0)—Offset 0h” on page 2864

00000000h

“SSP Control 1 Register (SSCR1)—Offset 4h” on page 2865

43000000h

“SSP Status Register (SSSR)—Offset 8h” on page 2867

0000F004h

“SSP Interupt Test Register (SSITR)—Offset Ch” on page 2869

00000000h

10h

“SSP Data Register (SSDR)—Offset 10h” on page 2869

00000000h

28h

“SSP Time-Out Regsiter (SSTO)—Offset 28h” on page 2870

00000000h

2Ch

“SSP Programmable Protocol Register (SSPSP)—Offset 2Ch” on page 2871

00000000h

30h

“SSM TX Time Slot Active Register (SSTSA)—Offset 30h” on page 2872

00000000h

34h

“SSP RX Time Slot Active Register (SSRSA)—Offset 34h” on page 2872

00000000h

38h

“SSP Time Slot Status Register (SSTSS)—Offset 38h” on page 2873

00000000h

3Ch

“SSP Audio Clock Divider (SSACD)—Offset 3Ch” on page 2873

00000000h

40h

“SSP Control 2 Register (SSCR2)—Offset 40h” on page 2874

000000C0h

44h

“SSP Frame Select Register (SSFS)—Offset 44h” on page 2875

00000001h

48h + [0-7]*4h

“SSP Slot Frame Counter Register[0-7] (FRAME_CNT[0-7])—Offset 48h, Count 8,

Stride 4h” on page 2876

00000000h

68h

“SSP FIFO Level Register (SFIFOL)—Offset 68h” on page 2877

FFFF0000h

6Ch

“SSP FIFO Trigger Threshold Register (SFIFOTT)—Offset 6Ch” on page 2877

00000000h

70h

“SSP Control 3 Register (SSCR3)—Offset 70h” on page 2878

0002C604h

74h

“SSP Control 4 Register (SSCR4)—Offset 74h” on page 2879

00000000h

78h

“SSP Control 5 Register (SSCR5)—Offset 78h” on page 2880

00000000h

7Ch

“ASRC Free Running Timer (ASRC_FRT)—Offset 7Ch” on page 2881

00000000h

80h

“Frame Threshold for ASRC Frame Count (ASRC_FTC)—Offset 80h” on page 2881

00000000h

84h

“ASRC Timer Snapshot (ASRC_SNPSHT)—Offset 84h” on page 2882

00000000h

88h

“ASRC Frame Count (ASRC_FRMCNT)—Offset 88h” on page 2882

00000000h

Type:

Memory Mapped I/O Register

(Size: 32 bits)

SSCR0:

[BAR + 0A0000h] + 0h

BAR Type:

PCI Configuration Register (Size: 32 bits)

BAR Reference:

[B:0, D:21, F:0] + 10h