Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2868
Datasheet
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0
RSVD
1
ASR
C
_
In
te
rr
u
p
t
BCE
CSS
TU
R
EO
C
TINT
PI
N
T
RSVD
2
RFL
TFL
ROR
RFS
TFS
BSY
RNE
TN
F
RSVD
3
Bit
Range
Default &
Access
Description
31:25
00h
RO
RSVD1:
Reserved
24
0b
RW/1C
ASRC Interrupt (ASRC_Interrupt):
The interrupt bit is set to 1 when the frame count
matches the frame threshold. This is Write 1 to clear register bit.
23
0b
RW/1C
Bit Count Error (BCE):
0 = SSP has not experienced a bit count error 1 = SSPSFRM
signal has been asserted when the bit counter was not 0
22
0b
RO
Clock Synchronization Status (CSS):
0 = SSP is ready for slave clock operations 1 =
SSP is currently busy synchronizing slave mode signals
21
0b
RW/1C
Transmit FIFO Under Run (TUR):
0 = Transmit FIFO has not experienced an under
run 1 = Attempted read from the transmit FIFO when the FIFO was empty, request
interrupt
20
0b
RW/1C
End of Chain (EOC):
0 = DMA has not signaled an end of chain condition 1 = DMA has
signaled an end of chain condition
19
0b
RW/1C
Receiver Time-out Interrupt (TINT):
0 = No receiver time-out pending 1 = Receiver
time-out pending
18
0b
RW/1C
Peripheral Trailing Byte Interrupt (PINT):
0 = No peripheral trailing byte interrupt
pending 1 = Peripheral trailing byte interrupt pending
17:16
00b
RO
RSVD2:
Reserved
15:12
1111b
RO
Receive FIFO Level (RFL):
Number of entries minus one in Receive FIFO. Note: When
the value 0xF is read, the FIFO is either empty or full and the programmer should refer
to the RNE bit. This is a legacy register and only represents the lower 4b of the FIFO
Level. The SFIFOL register contains the full FIFO level status.
11:8
0000b
RO
Transmit FIFO Level (TFL):
Number of entries in Transmit FIFO. Note: When the
value 0x0 is read, the FIFO is either empty or full and the programmer should refer to
the TNF bit. This is a legacy register and only represents the lower 4b of the FIFO Level.
The SFIFOL register contains the full FIFO level status.
7
0b
RW/1C
Receive FIFO Overrun (ROR):
0 = Receive FIFO has not experienced an overrun 1 =
Attempted data write to full receive FIFO, request interrupt
6
0b
RO
Receive FIFO Service Request (RFS):
0 = Receive FIFO level is at or below RFT
threshold (RFT), or SSP disabled 1 = Receive FIFO level exceeds RFT threshold (RFT),
request interrupt
5
0b
RO
Transmit FIFO Service Request (TFS):
0 = Transmit FIFO level exceeds the TFT
threshold (TFT+1), or SSP disabled 1 = Transmit FIFO level is at or below TFT threshold
(TFT+1), request interrupt
4
0b
RO
SSP Busy (BSY):
0 = SSP is idle or disabled 1 = SSP currently transmitting or receiving
a frame
3
0b
RO
Receive FIOF Not Empty (RNE):
0 = Receive FIFO is empty 1 = Receive FIFO is not
empty
2
1b
RO
Transmit FIFO Not Full (TNF):
0 = Transmit FIFO is full 1 = Transmit FIFO is not full