Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2874

Datasheet

SSPSFRM frequency. Note that Writes to reserved bits must be zeroes, and Read value 

of these bits are undetermined. It's important to note that this feature is only available 

if implemented by the project instantiation. A clock source and mux must be 

instantiated outside of the SSP controller for this feature to work. Only this register is 

designed into the SSP Controller.

Default: 00000000h

The command status register 2 is extension of command status register and contains 

various feature enable and disables.

Default: 000000C0h

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:21, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RS

VD

AC

PS

SC

DB

AC

DS

31:7

0000000h

RO

Reserved

6:4

000b

RW

Value indicates which PLL output clock is sent to the 

clock divider in the clock unit 000: 5.622MHz, 001: 11.345MHz, 010: 12.235MHz, 011: 

14.857MHz, 100: 32.842MHz, 101: 48.000MHz, 110, 111: Reserved

3

0b

RW

0 = SYSCLK is divided by 4 before being sent to SSP 

1 = SYSCLK is not divided before being sent to SSP

2:0

000b

RW

Value indicates which divider will be used by the 

clock unit to create the SYSCLK output pin. Clock divider value will be 2^ACDS, max 

ACDS = 5.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:21, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0

RS

VD0

A

S

RC_INTR_MA

SK

ASR

C

_

FR

M_CNT

R

_E

N

AS

RC_

C

NTR_CLR

A

S

RC_CNTR_EN

FIFO_E

M

PTY

_FIX_EN

UNDRN_FIX_EN

Re

se

rv

ed

C

LK_DE

L_EN

SL

V

_

EXT_C

LK_RUN_EN

Und

err

un_fix_1

Und

err

un_fix_0