Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2875
21.12.13 SSP Frame Select Register (SSFS)—Offset 44h
The SSP Frame select register is used to choose which frame signal to assert when
accessing a slave device. SW drivers should set this register to assert the correct frame
select to the targetted device.
Access Method
Default: 00000001h
Bit
Range
Default &
Access
Description
31:12
0b
RO
RSVD0:
Reserved
11
0b
RW
ASRC Interrupt Mask (ASRC_INTR_MASK):
Setting this bit to 1 masks the ASRC
interrupt that is generated every time the frame count matches the frame threshold.
Software should override this bit, since it have no reset value
10
0b
RW
ASRC frame count enable (ASRC_FRM_CNTR_EN):
Setting this bit enables the
frame counter to start running. Clearing this bit will make the frame counter go back to
zero immediately.
9
0b
RW/AC
ASRC Counter Clear (ASRC_CNTR_CLR):
Setting this to 1 will clear the ASRC Free
running counter. This bit will self clear after the counter is cleared.
8
0b
RW
ASRC Counter enable (ASRC_CNTR_EN):
Setting this bit makes the Free running
ASRC counter to start running. Clearing this bit will make it pause and hold it's current
value.
7
1b
RW
Fifo empty fix enable (FIFO_EMPTY_FIX_EN):
Corner cases between the FIFO
empty and APB writes happening to the TX FIFO around the time the new data needs to
be sent out on the TXD are fixed with this bit.
6
1b
RW
Underrun fix enable (UNDRN_FIX_EN):
OSC to PLL switch along with underrun was
causing unexpected behavior. This bit enables the fix for that bug.
5:4
00b
RW
Reserved:
This is a RW bit with no effect on IP behavior
3
0b
RW
Clock Delay Enable (CLK_DEL_EN):
When CLK_DEL_EN = 0, delay logic for
capturing data from device is disabled. When CLK_DEL_EN = 1, delay logic for capturing
data from device is delayed by half a period of the IO clock
2
0b
RW
Slave Mode External Clock Run Enable (SLV_EXT_CLK_RUN_EN):
When in Slave
mode the receive state machine requires several clock edges (around 6) to properly
sample incoming data. This bit enables a free running clock to the receive state machine
before any data is received to properly sample the incoming data. 0 = Disable 1 =
Enable
1
0b
RW
Mode 1 Underrun Fix (Underrun_fix_1):
Mode 1 of transmit underrun fix. In this
mode, new data will start on the underrun slot. This function is only appled to TI and
PSP modes. 0 = disable mode 1 1 = enable mode 1 If both underrun modes are enable,
mode 1 has higher priority.
0
0b
RW
Mode 0 Underrun Fix (Underrun_fix_0):
Mode 0 of transmit underrun fix. In this
mode, new data will always start at slot 0. This function is only applied to TI and PSP
modes. 0 = disable mode 1 1 = enable mode 1
Type:
Memory Mapped I/O Register
(Size: 32 bits)
SSFS:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h