Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2878
Datasheet
21.12.17 SSP Control 3 Register (SSCR3)—Offset 70h
Software should only program this register if configuring the SSP in I2S/LJ mode or
PCM master mode with the Tangier fixes. If neither is being enabled, SW can leave this
register at the default power on value.
Access Method
Default: 0002C604h
Bit
Range
Default &
Access
Description
31:16
0000h
RW
Receive FIFO Trigger Threshold (RFT):
Sets threshold level at which receive FIFO
asserts interrupt. This level should be set to the desired threshold value minus 1. Notes
on setting the RFT value. This applies to cases where SSP is receiving data from a
device and is interfaced with a DMA channel via the hardware handshake mechanism.
Please follow the following recommendations: 1. Number of bits denoted by the (DSS,
EDSS) parameters in the SSP should match the SRC_TR_WIDTH programmed in the
DMA channel. 2. (RFT+1) should be equal to (SRC_MSIZE). 3. Another option to 2 is to
keep the BLOCK_TS in the DMA to be a multiple of (RFT+1)
15:0
0000h
RW
Transmit FIFO Trigger Threshold (TFT):
Sets threshold level at which transmit FIFO
asserts interrupt. This level should be set to the desired threshold value minus 1.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
SSCR3:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 0 0 1 0 0
RSV
D
0
SY
N_FIX_E
N
MST_CLK_EN
STRE
TC
H_RX
ST
R
E
TC
H
_
T
X
RSVD
RSVD
I2S
_
VISA
_EN
I2S_RX_EN
I2S_TX_EN
RSVD
RSVD
RSVD
I2S_RX
_S
S_FIX_E
N
I2S_TX
_S
S_FIX_E
N
RSVD
I2S_MODE_EN
FRM_MST_E
N
Bit
Range
Default &
Access
Description
31:18
0b
RO
RSVD0:
Reserved
17
1b
RW
Sync Fix Enable (SYN_FIX_EN):
This is a chicken bit for enabling the synchronizer fix
for clr_underrun_ssp signal. SW should preserve this bit at its default value.
16
0b
RW
Master Mode Clock Enable (MST_CLK_EN):
When in single slot master mode (which
is the mode used for emulating I2S or LJ master mode), the SSP core can stop the clock
on a Tx underflow condition, preventing the Rx side from receiving data. This bit, when
set, forces the clock to run when a Tx underflow happens, thereby allowing Rx side to
continue functioning while Tx side is in underflow. SW should set this bit when I2S or LJ
master mode is enabled i.e. bits 0 and 1 in this register are both set or when using 1-
slot PCM (SFS or LFS) master mode operation. Otherwise, SW should leave this at 0.
15
1b
RW
Stretch RX Pulse (STRETCH_RX):
HW uses this as a chicken bit to stretch the RX
pulse for proper clock crossing between SSP and APB domains. Note this bit is not tied
to any specific SSP/PCM/I2S modes. SW should preserve this bit as the default value.
14
1b
RW
Stretch TX Pulse (STRETCH_TX):
HW uses this as a chicken bit to stretch the TX
pulse for proper clock crossing between SSP and APB domains. Note this bit is not tied
to any specific SSP/PCM/I2S modes. SW should preserve this bit as the default value.