Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2879

Software should only program this register if configuring the SSP in I2S/LJ mode or 

PCM master mode with the Tangier fixes. If neither is being enabled, SW can leave this 

register at the default power on value.

13

0b

RO

Reserved.

12

0b

RO

Reserved.

11

0b

RW

Enables newly added I2S and PCM wrapper logic 

debug signals sent out on the VISA bus instead of the core SSP debug signals. 0 = Core 

SSP Debug Signals 1 = New I2S and PCM Debug Signals

10

1b

RW

When set, this bit enables data to be received on 

both the left and right slots of I2S. Otherwise, data on the slots are ignored. HW does 

not signal FIFO full condition when this bit is cleared. SW can set/clear this bit 

dynamically when I2S mode is operational.

9

1b

RW

When set, this bit enables data to be transmitted 

on both the left and right slots of I2S. Otherwise, data on the slots are ignored. HW 

does not signal FIFO full condition when this bit is cleared. SW can set/clear this bit 

dynamically when I2S mode is operational.

8

0b

RO

Reserved.

7:6

00b

RO

Reserved.

5

0b

RO

Reserved.

4

0b

RW

This bit enables the Rx 

overrun fix in I2S or LJ modes and prevents channel swapping when Rx overrun 

happens. Note that this bit does not apply to any PCM modes. PCM modes still have the 

Rx overflow channel aliasing issue, similar to PNW/CLV. SW should set this bit only when 

I2S or LJ mode (slave or master) is enabled. 0 = Disable 1 = Enable

3

0b

RW

This bit enables the TX 

underflow fix in I2S or LJ modes and prevents channel swapping when TX underflow 

happens. Note that this bit does not apply to any PCM modes. PCM modes still have the 

TX underflow channel aliasing issue, similar to PNW/CLV. SW should set this bit only 

when I2S or LJ mode (slave or master) is enabled. 0 = Disable 1 = Enable

2

1b

RO

Reserved.

1

0b

RW

This bit enables I2S Mode. In I2S mode, slave or 

master mode operation is selected by appropriately clearing/setting bit 0 in this register. 

SW should select I2S mode operation before enabling the SSP controller. 0 = Disabled 1 

= Enabled

0

0b

RW

When set, this bit enables the internal frame 

generator logic that allows accurate frame rate generation. This bit should be set for I2S 

and PCM master mode operations and cleared for all other modes. SW should select the 

proper value in this bit before enabling SSP controller. 0 = Disabled 1 = Enabled

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:21, F:0] + 10h