Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2885
21.13.2
SSP Control 1 Register (SSCR1)—Offset 4h
The Enhanced SSP Control 1 registers contain bit fields that control various SSP
functions. Bits must be set to the preferred value before enabling the Enhanced SSP.
Note that Writes to reserved bits should be zeroes, and Read value of these bits are
undetermined.
Access Method
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MOD
AC
S
RSVD
RSVD
RSVD
FRDC
TI
M
RIM
NC
S
ED
S
S
SC
R
SS
E
EC
S
FRF
DSS
Bit
Range
Default &
Access
Description
31
0b
RW
Mode Select (MOD):
0 = Normal SSP Mode 1 = Network Mode
30
0b
RW
Audio Clock Select (ACS):
0 = Clock selection is determined by the NCS and ECS bits
1 = Audio Clock (and Audio Clock Divider) are used to clock the SSP's serial clock
(SSPSCLK)
29
0b
RO
Reserved (RSVD):
Reserved.
28
0b
RO
Reserved (RSVD):
Reserved.
27
0b
RO
Reserved (RSVD):
Reserved.
26:24
000b
RW
Frame Rate Divider Control (FRDC):
Value 0-7 indicates the number of time slots per
frame when in network mode (the actual number of time slots is FRDC+1, so 1 to 8 time
slots).
23
0b
RW
Transmit FIFO Under Run Interrupt Mask (TIM):
0 = TUR events will generate an
SSP interrupt 1 = TUR events will not generate an SSP interrupt
22
0b
RW
Receive FIFO Over Run Interrupt Mask (RIM):
0 = ROR events will generate an
SSP interrupt 1 = ROR events will not generate an SSP interrupt
21
0b
RW
Network Clock Select (NCS):
0 = Clock selection is determined by ECS bit 1 =
Network clock is used to create the SSP's serial clock (SSPSCLK)
20
0b
RW
Extended Data Size Select (EDSS):
0 = A zero is preappended to the DSS value
which sets the DSS range from 4-16 bits 1 = A one is pre-appended to the DSS value
which sets the DSS range from 17-32 bits
19:8
000h
RW
Serial Clock Rate (SCR):
Value (0 to 4095) used to generate transmission rate of SSP.
Serial bit rate = SSP clock/(SCR+1), where SCR is decimal integer.
7
0b
RW
Synchronous Serial Port Enable (SSE):
0 = SSP operation disabled and FIFOs are
cleared 1 = SSP operation enabled
6
0b
RW
External Clock Select (ECS):
0 = On-chip clock used to produce the SSP's serial clock
(SSPSCLK) 1 = SSPEXTCLK/GPIO pin is used to create the SSP's SSPCLK
5:4
00b
RW
Frame Format (FRF):
00 = Motorola Serial Peripheral Interface (SPI) 01 = Texas
Instruments Synchronous Serial Protocol (SSP) 10 = National Semiconductor Microwire
11 = Programmable Serial Protocol (PSP)
3:0
0000b
RW
Data Size Select (DSS):
With EDSS as MSB, value+1 gives data size. Values 4 to 32
allowed.