Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2886
Datasheet
Default: 43000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
SSCR1:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TT
E
LP
TT
E
E
B
CE
I
SC
FR
EC
RA
EC
RB
SC
LKDIR
SFRMDIR
RWO
T
TR
A
IL
TSR
E
RS
RE
TI
N
T
E
PINTE
RS
VD
IFS
STRF
EFWR
RF
T
TF
T
MWDS
SP
H
SP
O
LBM
TIE
RIE
Bit
Range
Default &
Access
Description
31
0b
RW
TXD Tristate Enable on Last Phase (TTELP):
0 = TXD line will be tristated on same
clock edge as TXD is to be flopped 1 = TXD line will be tristated 1/2 clock edge after
TXD is to be flopped
30
1b
RW
TXD Tristate Enable (TTE):
0 = TXD line will not be tristated 1 = TXD line will be
tristated when no transmitting data
29
0b
RW
Enable Bit Count Error Interrupt (EBCEI):
0 = Interrupt due to a bit count error is
disabled 1 = Interrupt due to a bit count error is enabled
28
0b
RW
Slave Clock Free Running (SCFR):
0 = clock input to SSPSCLK is continuously
running 1 = clock input to SSPSCLK is only active durring transfers
27
0b
RW
Enable Clock Request A (ECRA):
0 = clock request from other SSP is disabled 1 =
clock request from other SSP is enabled
26
0b
RW
Enable Clock Request B (ECRB):
0 = clock request from other SSP is disabled 1 =
clock request from other SSP is enabled
25
1b
RW
SSP Serial Bit Rate Clock (SSPSCLK) Direction (SCLKDIR):
0 = Master mode, SSP
drives SSPSCLK 1 = Slave mode, SSP recieves SSPSCLK
24
1b
RW
SSP Frame (SSPSFRM) Direction (SFRMDIR):
0 = Master mode, SSP drives
SSPSFRM 1 = Slave mode, SSP receives SSPSFRM
23
0b
RW
Receive With Out Transmit (RWOT):
0 = Transmit/Receive mode 1 = Receive
without transmit mode
22
0b
RW
Trailing Byte (TRAIL):
0 = Processor based, trailing bytes are handled by processor 1
= DMA based, trailing bytes are handled by DMA
21
0b
RW
Transmit Service Request Enable (TSRE):
0 = DMA Service Request is disabled 1 =
DMA Service Request is enabled
20
0b
RW
Receive Service Request Enable (RSRE):
0 = DMA Service Request is disabled 1 =
DMA Service Request is enabled
19
0b
RW
Receiver Time-out Interrupt Enable (TINTE):
0 = Receiver Time-out interrupts are
disabled 1 = Receiver Time-out interrupts are enabled
18
0b
RW
Peripheral Trailing Byte Interrupts Enable (PINTE):
0 = Peripheral Trailing Byte
Interrupts are disabled 1 = Peripheral Trailing Byte Interrupts are enabled
17
0b
RW
RSVD:
Reserved
16
0b
RW
Invert Frame Signal (IFS):
0 = Frame polarity is determined by SSP format and PSP
polarity bits 1 = Frame signal will be inverted from the normal SSP frame signal (as
defined by the SSP format nad PSP polarity bits)