Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
289
12.3.6
DTR4 (DTR4)—Offset 5h
DRAM Timing Register 4
Access Method
Default: 00003322h
16:13
3h
RW
tWRSR:
Write to Read same rank command delay. Should be set to 4 + tWCL + tWTR
0h - 11 DRAM Clocks (LPDDR2-800) 1h - 12 DRAM Clocks 2h - 13 DRAM Clocks (DDR3-
800. LPDDR2-1066) 3h - 14 DRAM Clocks (DDR3-1066) 4h - 15 DRAM Clocks 5h - 16
DRAM Clocks (DDR3-1333. LPDDR3-1333) 6h - 17 DRAM Clocks 7h - 18 DRAM Clocks
(DDR3-1600) 8h - 19 DRAM Clocks 9h - 20 DRAM Clocks Others - Reserved
12
0h
RO
Rsvd_12_DTR3:
Reserved
11:8
2h
RW
tRWSR:
Read to Write same rank command delay. Should be set to tCL - tWCL + 6 +
board delay if needed. 0h - 6 DRAM Clocks (DDR3) 1h - 7 DRAM Clocks 2h - 8 DRAM
Clocks 3h - 9 DRAM Clocks 4h - 10 DRAM Clocks 5h - 11 DRAM Clocks (LPDDR2-800) 6h
- 12 DRAM Clocks (LPDDR2-1066) 7h - 13 DRAM Clocks 8h - 14 DRAM Clocks 9h - 15
DRAM Clocks (LPDDR3-1333) Ah - 16 DRAM Clocks Bh - 17 DRAM Clocks Others -
Reserved
7
0h
RO
Rsvd_7_DTR3:
Reserved
6:4
5h
RW
tWRDD:
Write to Read DQ delay, different DIMMs 0h - 4 DRAM Clocks (LPDDR3-1333)
1h - 5 DRAM Clocks (LPDDR2-800, 1066) 2h - 6 DRAM Clocks (DDR3) 3h - 7 DRAM
Clocks 4h - 8 DRAM Clocks 5h - 9 DRAM Clocks 6h - 10 DRAM Clocks Others - Reserved
3
0h
RO
Rsvd_3_DTR3:
Reserved
2:0
5h
RW
tWRDR:
Write to Read DQ delay, different ranks, same DIMM 0h - Reserved 1h - 4
DRAM Clocks (LPDDR3-1333) 2h - 5 DRAM Clocks (LPDDR2-800, 1066) 3h - 6 DRAM
Clocks (DDR3) 4h - 7 DRAM Clocks 5h - 8 DRAM Clocks 6h - 9 DRAM Clocks 7h - 10
DRAM Clocks
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Message Bus Register
(Size: 32 bits)
Offset:
Op Codes:
h - Read, h - Write
h - Read, h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 0 0 1 0
Rsvd_31_
19_D
TR
4
WRBO
D
T
DIS
RDO
D
TDIS
TR
G
S
T
R
D
IS
Rsvd_
15_D
TR
4
RD
O
D
TS
TO
P
Rsvd
_24
RDOD
T
S
TR
T
Rsvd_7_D
TR
4
WROD
T
S
TO
P
Rsvd_3
_2_D
TR
4
WROD
T
S
TR
T