Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
290
Datasheet
12.3.7
DPMC0 (DPMC0)—Offset 6h
DRAM Power Management Control 0
Access Method
Default: 0B000000h
Bit
Range
Default &
Access
Field Name (ID): Description
31:19
0h
RO
Rsvd_31_19_DTR4:
Reserved
18
0h
RW
WRBODTDIS:
Disable Write ODT on non-targeted DIMM. When writing to DIMM A, ODT
is asserted to the target rank of DIMM A and also to the low rank of DIMM B. This
defeature bit is used to disable ODT assertion to the opposite DIMM during write.
17
0h
RW
RDODTDIS:
Disable Read ODT. When reading from DIMM A, ODT is asserted to the low
rank of DIMM B. This defeature bit is used to disable ODT assertion during reads.
16
0h
RW
TRGSTRDIS:
Write target rank is not stretched. When set, stretched ODT as defined
above is not applied to the write target rank and ODT command is asserted for 6 DRAM
clocks. Should not be used when ODT is pulled-in.
15
0h
RO
Rsvd_15_DTR4:
Reserved
14:12
3h
RW
RDODTSTOP:
Read command to ODT de-assert delay Value should be set to:
RDODTSTRT+6+(WRODTSTOP-WRODTSTRT) 0h - 6 DRAM Clocks 1h - 7 DRAM Clocks
2h - 8 DRAM Clocks 3h - 9 DRAM Clocks 4h - 10 DRAM Clocks 5h - 11 DRAM Clocks 6h -
12 DRAM Clocks 7h - 13 DRAM Clocks Other - Reserved
11
0h
RO
Rsvd_24:
Reserved
10:8
3h
RW
RDODTSTRT:
Read command to ODT assert delay. Value should be set to tCMD+tCL-
tWCL-ODT_PULLIN, where ODT_PULLIN must have the same value as in WRODTSTRT.
0h - 0 DRAM Clocks 1h - 1 DRAM Clocks 2h - 2 DRAM Clocks 3h - 3 DRAM Clocks 4h - 4
DRAM Clocks 5h - 5 DRAM Clocks Other - Reserved
7
0h
RO
Rsvd_7_DTR4:
Reserved
6:4
2h
RW
WRODTSTOP:
Write command to ODT de-assert delay. WRODTSTOP 1N 2N 3N 0h
WR+6 N/A N/A 1h WR+7 WR+6 N/A 2h WR+8 WR+7 WR+6 3h WR+9 WR+8 WR+7 4h
WR+10 WR+9 WR+8 Other Reserved Reserved Reserved
3:2
0h
RO
Rsvd_3_2_DTR4:
Reserved
1:0
2h
RW
WRODTSTRT:
WR command to ODT assert delay. JEDEC requires ODT to be asserted
on the same clock with the WR command. Dunit allows to pull-in by 1 clock in 2N mode
and by 1-2 clocks in 3N mode. For most DIMM configurations, this register should be
programmed to same value as tCMD. A value of tCMD - ODT_PULLIN can be used
according to the table below which shows the ODT command assertion with respect to
the WR command assertion. WRODTSTRT 1N 2N 3N 0h WR WR-1 WR-2 1h N/A WR WR-
1 2h N/A N/A WR 3h Reserved Reserved Reserved
Type:
Message Bus Register
(Size: 32 bits)
Offset:
Op Codes:
h - Read, h - Write
h - Read, h - Write