Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

292

Datasheet

DRAM Power Management Control 1

Default: 00000011h

20

0h

RW

Wake Allowed for Page Close Timeout. Setting this bit to 1 indicates the 

Dunit can send DRAM devices a PD-Exit command in order to close single bank if the 

page timer expired. Note: This bit applies only to cases where at least one other bank in 

the same rank is open but not timed-out. If all banks in the rank timed-out, a PD-Exit 

command will be sent regardless of this bit. Must be set to 0 during init/training mode. 

0h - Disable 1h - Enable

19

0h

RO

Reserved

18:16

0h

RW

Page Close Timeout Period. Specifies the time frame, in ns, from last access to 

a DRAM page until that page may be scheduled for closing (by sending a PRE 

command). 0h - Disable page close timer (init/training) 1h - Immediate page close 2h - 

30-60 ns to page close 3h - 60-120 ns to page close 4h - 120-240 ns to page close 5h - 

240-480 ns to page close 6h - 480-960 ns to page close 7h - 1-2 s to page close 

15:13

0h

RO

Reserved

12:8

0h

RW

SPID Power Mode Opcode. The PM Message ID the Dunit will send to DDRIO on 

ispid_pm_pm bus after SR Entry command to DRAM. This message defines the DDRIO 

power-mode during SR period. Value can be changed on-the-fly to allow different power 

modes (for example, deeper PM for S3 than for C6). Power saving and Entry/Exit 

latencies are described in the MODMEM HAS. 

7:0

0h

RW

Self-Refresh Entry delay. The delay, in core-clocks, between PMI idle (no 

pending requests and PMI status is less than 2) and SR Entry when Dunit is in Dynamic 

SR mode. 

Message Bus Register

(Size: 32 bits)

Op Codes:
h - Read, h - Write

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1

Rs

vd_31_6_DPM

C1

CM

D

T

R

IST

Rs

vd_3_1_DPM

C1

CS

TRIS

T

31:6

0h

RO

Reserved