Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

300

Datasheet

DRAM CB Register

Default: 00000000h

15:14

0h

RW/L

Command/Address Training Mask Mask data for comparison. 0h - No Mask 

1h - Mask out data from byte[1] and byte[4] 2h - Mask out data from upper 32bits 3h - 

Mask both bytes and upper 32bits

13:12

0h

RW/L

Command/Address Training Loop Count

11

0h

RO

Reserved

10:9

0h

RW/L

Command/Address Training Rank Select 0h - Rank 0 (DIMM0) is selected 1h - 

Rank 1 (DIMM0) is selected 2h - Rank 2 (DIMM1) is selected 3h - Rank 3 (DIMM1) is 

selected

8

0h

RW/P/L

Command/Address Training Start Set this bit to 1 to start CA training. This 

bit will remain a 1 until CA training is complete, then it will return to 0. 0 - CA Training is 

done 1 - CA Training has started and is in progress Note: This is an LPDDR feature only.

7:6

0h

RO

Reserved

5

0h

RW/L

Block All PhaseB Commands. Dunit operates at coreclock which is half the 

frequency of the DRAM clock. When this bit is set, only one command can be scheduled 

each coreclock. This bit may be used for DFX applications.

4

0h

RW/L

Block all IP Requests until Queue is Full. When this bit is set to 1, all Dunit 

are stalled until the IP pool is full. This bit is self-clearing, and once asserted, writing 0 

has no impact. The IPREQ pool is only reopened when the number of pending requests 

reaches DSCH.IPREQMAX+1.

3

0h

RW/L

Block Precharge Commands to DRAM 0 - No Block 1 - Block

2

0h

RW/L

Block Activate Commands to DRAM 0 - No Block 1 - Block

1

0h

RW/L

Block Write Commands to DRAM 0 - No Block 1 - Block

0

0h

RW/L

Block Read Commands to DRAM 0 - No Block 1 - Block

Message Bus Register

(Size: 32 bits)

Op Codes:
h - Read, h - Write

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Rsvd_3

1_9_DCBR

SRXNRQ

DIS

Rsvd_

7_2_DCBR

DMINV

PHS

INV