Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
306
Datasheet
12.3.26
BONUS0 (BONUS0)—Offset 50h
Bonus Register 0
Access Method
Default: 00000000h
12.3.27
BONUS1—Offset 51h
Bonus Register 1
Access Method
Default: 00000000h
Type:
Message Bus Register
(Size: 32 bits)
Offset:
Op Codes:
h - Read, h - Write
h - Read, h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rsvd_31_
4_BONU
S
0
LP
D
D
RCM
D
T
R
I
MRRCMDDL
Y
CA
TBU
G
FI
X
SL
O
W
PD
XE
N
PE
RFMO
NEN
DIS
E
ARL
Y
SRX
Bit
Range
Default &
Access
Field Name (ID): Description
31:7
0h
RO
Rsvd_31_7_BONUS0 (Rsvd_31_4_BONUS0):
Reserved
6
0h
RW
LPDDRCMDTRI:
Enable LPDDR CMD Tri-Stating
5:4
0h
RW
MRRCMDDLY:
Adding addtional delay on MRR followed by read and write command
3
0h
RW
CATBUGFIX:
This is a defeature bit for CA training and should be set to 0 for normal
operation.
2
0h
RW
SLOWPDXEN:
This bit is for enabling slow powerdown exit.
1
0h
RW
PERFMONEN:
This bit is for enabling performance monitor.
0
0h
RW
DISEARLYSRX:
This bit is for enabling early SR exit.
Type:
Message Bus Register
(Size: 32 bits)
Offset:
Op Codes:
h - Read, h - Write
h - Read, h - Write