Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
307
12.3.28
DECCCTRL (DECCCTRL)—Offset 60h
DECC Control Register
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BO
NU
S
1
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0h
RW
BONUS1:
Bonus Register 1 (This register is reserved for ECO).
Type:
Message Bus Register
(Size: 32 bits)
Offset:
Op Codes:
h - Read, h - Write
h - Read, h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rsvd_31_
18_DE
C
C
C
TRL
ENC
B
GE
N
Rsvd_
16_DE
C
C
C
TRL
CBO
V
CLRS
BEC
N
T
SY
NS
EL
CBO
E
N
D
B
EEN
S
B
EEN
Bit
Range
Default &
Access
Field Name (ID): Description
31:18
0h
RO
Rsvd_31_18_DECCCTRL:
Reserved
17
0h
RW
ENCBGEN:
DFx: Enable Generation of ECC check bits 0 - Disable check bit generation 1
- Enable check bit generation
16
0b
RO
Rsvd_16_DECCCTRL:
Reserved
15:8
00h
RW
CBOV:
DFx: Check Bit Override (Host Defined Value)
7
00h
RW
CLRSBECNT:
DFx: Clear SERR counter 0 - Allow single bit error count to increment 1 -
Clear single bit error count
6:5
00h
RW
SYNSEL:
DFx: Select syndrome bits from 256b read data path. 0h - Selects syndrome
bits from read data [63:0] 1h - Selects syndrome bits from read data [127:64] 2h -
Selects syndrome bits from read data [191:128] 3h - Selects syndrome bits from read
data [255:192]