Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
314
Datasheet
12.3.39
PMAUXMIN—Offset E9h
Performance Monitor Address Limit Low
Access Method
Default: 00000000h
12.3.40
PMAUX (PMAUX)—Offset EAh
Performance Monitor Aux
Access Method
Default: 00000000h
27:0
0h
RW
MAX:
Maximal address or maximal latency count. When PMSEL0.EVTID == Ch, this
register should be initialized to 0h and at the end of the test bits [11:0] will contain the
max latency. When PMSEL0/1/2.EVTID == 5h, this register should be initialized to the
highest address the Perfmon test will cover. Bits [27:0] of this register correspond to the
physical address bits [32:8].
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Message Bus Register
(Size: 32 bits)
Offset:
Op Codes:
h - Read, h - Write
h - Read, h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rsvd_31_
28_PMAU
X
M
IN
MI
N
Bit
Range
Default &
Access
Field Name (ID): Description
31:28
0h
RO
Rsvd_31_28_PMAUXMIN:
Reserved
27:0
0h
RW
MIN:
Minimal address or minimal latency count. When PMSEL0.EVTID == Ch, this
register should be initialized to FFFh and at the end of the test bits [11:0] will contain
the min latency. When PMSEL0/1/2.EVTID == 5h, this register should be initialized to
the lowest address the Perfmon test will cover. Bits [27:0] of this register correspond to
the physical address bits [32:8].
Type:
Message Bus Register
(Size: 32 bits)
Offset:
Op Codes:
h - Read, h - Write
h - Read, h - Write