Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
359
13.6.9
PUNIT_S0i3_PREWAKE—Offset 1Fh
BIOS or OS can program this register with a pre-wake value in Guaranteed MCLKs to
hide some of the exit latency from S0i3 state to S0 state. P unit will subtract this value
from the actual deadline programmed by the OS when requesting for a timer wake.
Access Method
Default: 00000000h
13.6.10
VEDSSPM0—Offset 32h
Subsystem Config/Status for VED
Access Method
Default: 03000003h
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0h
RW
s0i2_PREWAKE:
BIOS or OS can program this register with a pre-wake value in
Guaranteed MCLKs to hide some of the exit latency from S0i2 state to S0 state. P unit
will subtract this value from the actual deadline programmed by the OS when requesting
for a timer wake.
Type:
Message Bus Register
(Size: 32 bits)
Offset:
Op Codes:
h - Read, h - Write
h - Read, h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
s0
i3_P
RE
W
A
KE
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0h
RW
s0i3_PREWAKE:
S0i3 Prewake Deadline
Type:
Message Bus Register
(Size: 32 bits)
Offset:
Op Codes:
h - Read, h - Write
h - Read, h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Re
se
rv
ed
_
1
VE
D
S
SS
Re
se
rv
ed
_
3
VEDIE
Re
se
rv
ed
_
5
Re
se
rv
ed
_
6
VE
D
S
S
C