Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
369
Default: 00000000h
13.6.20
PTMC—Offset 80h
Programmable Thermtrip Management Control
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESE
RVED
_4
PO
C_
N
U
M
_
CO
R
E
S
RESE
RVED
_2
PO
C_
R
U
N
_
BI
ST
Bit
Range
Default &
Access
Field Name (ID): Description
31:11
0h
RO
RESERVED_4:
Reserved
10:8
0h
RW
POC_NUM_CORES:
Core defeature via BIOS...000b Do not defeature IA cores...001b
Only 1 Logical Core is active...010b Only 2 Logical Cores are active...011b Only 3 Logical
Cores are active...1xxb Reserved (for 8 Core config).. ..Exposed to CPU microcode as
CLPU_CR_RESOLVED_CORE_VECTOR, CLPU_CR_RESOLVED_CORE_VECTOR and
CLPU_CR_WHO_AM_I via RESET_CONFIG_CW (CPU PMlink space)... ..Punit will
determine the RESOLVED_CORE_VECTOR based on the table in HSD Issue 1214773...
7:1
0h
RO
RESERVED_2:
Reserved
0
0h
RW
POC_RUN_BIST:
Writing a 1 will cause the CPU microcode to execute BIST on the L2$
at CPU reset deassertion (CPU only reset or Warm Reset).
Type:
Message Bus Register
(Size: 32 bits)
Offset:
Op Codes:
h - Read, h - Write
h - Read, h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RE
S
E
R
V
E
D
_
1
CPU
_
MO
D1
MOD0_THERM_E
N
RE
S
E
R
V
E
D
_
4
SW
_TR
IG
G
E
R
BW_THRO
T
_E
N
XX
TT
S
_
T
H
E
R
M
_
EN
PRO
C
H
O
T_TH
ERM_E
N
SVID
V
R_IC
C_E
N
SVID_TH
ERM_E
N
RESE
RVED
_11
AUX3_THERM_E
N
AUX2_THERM_E
N
AUX1_THERM_E
N
AUX0_THERM_E
N
Bit
Range
Default &
Access
Field Name (ID): Description
31:18
0h
RO
RESERVED_1:
Reserved